Add STM32TS60 support

This chip got small flash and RAM, so the common runtime is disabled.
Now the code only boots and print something every second to check debug
console and timer are good.

BUG=None
TEST=Boot and see console output
TEST=make buildall
BRANCH=None

Change-Id: I01150e8250a404628d1a3b81e677ac4c29782d7f
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/195382
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

13 files changed, 533 insertions, 0 deletions

diff --git a/board/keyborg/board.c b/board/keyborg/board.c
new file mode 100644
index 0000000000..c21510530f
--- /dev/null
+++ b/board/keyborg/board.c
@@ -0,0 +1,26 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Keyborg board-specific configuration */
+
+#include "board.h"
+#include "common.h"
+#include "debug.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+int main(void)
+{
+	int i = 0;
+	hardware_init();
+	debug_printf("Keyborg starting...\n");
+
+	while (1) {
+		i++;
+		task_wait_event(SECOND);
+		debug_printf("Timer check - %d seconds\n", i);
+	}
+}
diff --git a/board/keyborg/board.h b/board/keyborg/board.h
new file mode 100644
index 0000000000..0acf810514
--- /dev/null
+++ b/board/keyborg/board.h
@@ -0,0 +1,39 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyborg board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* Optional features */
+#define CONFIG_DEBUG_PRINTF
+#undef CONFIG_ADC
+#undef CONFIG_COMMON_GPIO
+#undef CONFIG_COMMON_PANIC_OUTPUT
+#undef CONFIG_COMMON_RUNTIME
+#undef CONFIG_COMMON_TIMER
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_DEBUG_EXCEPTIONS
+#undef CONFIG_DEBUG_STACK_OVERFLOW
+#undef CONFIG_FLASH
+#undef CONFIG_FMAP
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TASK_PROFILING
+#undef CONFIG_WATCHDOG_HELP
+
+#ifndef __ASSEMBLER__
+
+enum gpio_signal;
+
+/* Initialize all useful registers */
+void hardware_init(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
diff --git a/board/keyborg/build.mk b/board/keyborg/build.mk
new file mode 100644
index 0000000000..d9f17bb5c3
--- /dev/null
+++ b/board/keyborg/build.mk
@@ -0,0 +1,13 @@
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32TS60
+CHIP:=stm32
+CHIP_FAMILY:=stm32f
+CHIP_VARIANT:=stm32ts60
+
+board-y=board.o hardware.o runtime.o
+board-$(CONFIG_DEBUG_PRINTF)+=debug.o
diff --git a/board/keyborg/debug.c b/board/keyborg/debug.c
new file mode 100644
index 0000000000..403af499c2
--- /dev/null
+++ b/board/keyborg/debug.c
@@ -0,0 +1,50 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* GPIO UART debug printf */
+
+#include "board.h"
+#include "common.h"
+#include "printf.h"
+#include "registers.h"
+#include "timer.h"
+#include "util.h"
+
+#define BAUD 9600
+#define BIT_PERIOD (1000000 / BAUD)
+
+int debug_txchar(void *context, int c)
+{
+	int i;
+	timestamp_t st;
+	int32_t d;
+
+	if (c == '\n')
+		debug_txchar(context, '\r');
+
+	c = (c << 1) | (1 << 9);
+	st = get_time();
+	for (i = 0; i < 10; ++i) {
+		STM32_GPIO_BSRR(GPIO_A) = 1 << ((c & 1) ? 15 : 31);
+		d = MAX(st.val + BIT_PERIOD * (i + 1) - get_time().val, 0);
+		if (d)
+			udelay(d);
+		c >>= 1;
+	}
+
+	return 0;
+}
+
+void debug_printf(const char *format, ...)
+{
+	va_list args;
+
+	va_start(args, format);
+	vfnprintf(debug_txchar, NULL, format, args);
+	va_end(args);
+}
+
+void panic(const char *msg)
+{
+}
diff --git a/board/keyborg/debug.h b/board/keyborg/debug.h
new file mode 100644
index 0000000000..a7ae4bfe8f
--- /dev/null
+++ b/board/keyborg/debug.h
@@ -0,0 +1,16 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* GPIO UART debug printf */
+
+#ifndef __BOARD_KEYBORG_DEBUG_H
+#define __BOARD_KEYBORG_DEBUG_H
+
+#ifdef CONFIG_DEBUG_PRINTF
+void debug_printf(const char *format, ...);
+#else
+#define debug_printf(...)
+#endif
+
+#endif /* __BOARD_KEYBORG_DEBUG_H */
diff --git a/board/keyborg/ec.tasklist b/board/keyborg/ec.tasklist
new file mode 100644
index 0000000000..e8860b4ebb
--- /dev/null
+++ b/board/keyborg/ec.tasklist
@@ -0,0 +1,19 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST
diff --git a/board/keyborg/hardware.c b/board/keyborg/hardware.c
new file mode 100644
index 0000000000..d6fa3755d0
--- /dev/null
+++ b/board/keyborg/hardware.c
@@ -0,0 +1,162 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Hardware initialization and common functions */
+
+#include "common.h"
+#include "cpu.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+static void clock_init(void)
+{
+	/* Ensure that HSI is ON */
+	if (!(STM32_RCC_CR & (1 << 1))) {
+		/* Enable HSI */
+		STM32_RCC_CR |= 1 << 0;
+		/* Wait for HSI to be ready */
+		while (!(STM32_RCC_CR & (1 << 1)))
+			;
+	}
+
+	/* PLLSRC = HSI/2, PLLMUL = x12 (x HSI/2) = 48MHz */
+	STM32_RCC_CFGR = 0x00684000;
+	/* Enable PLL */
+	STM32_RCC_CR |= 1 << 24;
+	/* Wait for PLL to be ready */
+	while (!(STM32_RCC_CR & (1 << 25)))
+			;
+
+	/* switch SYSCLK to PLL */
+	STM32_RCC_CFGR = 0x00684002;
+	/* wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+}
+
+static void power_init(void)
+{
+	/* enable ADC1, ADC2, PMSE, SPI1, GPA-GPI, AFIO */
+	STM32_RCC_APB2ENR = 0x0000f7fd;
+	/* enable TIM2, TIM3, PWR */
+	STM32_RCC_APB1ENR = 0x10000003;
+	/* enable DMA, SRAM */
+	STM32_RCC_AHBENR  = 0x000005;
+}
+
+/* GPIO setting helpers */
+#define OUT(n)    (0x1 << ((n & 0x7) * 4))
+#define OUT50(n)  (0x3 << ((n & 0x7) * 4))
+#define ANALOG(n) (0x0)
+#define FLOAT(n)  (0x4 << ((n & 0x7) * 4))
+#define GP_PP(n)  (0x0)
+#define GP_OD(n)  (0x4 << ((n & 0x7) * 4))
+#define AF_PP(n)  (0x8 << ((n & 0x7) * 4))
+#define AF_OD(n)  (0xc << ((n & 0x7) * 4))
+
+static void pins_init(void)
+{
+	/* Enable SWD, but disable JTAG. We want JTDI as GPIO. */
+	STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x7 << 24))
+			       | (2 << 24);
+
+	/* Pin usage:
+	 * PA15: UART TX - OUTPUT/HIGH
+	 */
+	STM32_GPIO_CRH(GPIO_A) = OUT(15) | GP_PP(15);
+}
+
+static void adc_init(void)
+{
+	int id;
+
+	for (id = 0; id < 2; ++id) {
+		/* Enable ADC clock */
+		STM32_RCC_APB2ENR |= (1 << (14 + id));
+
+		/* Power on ADC if it's off */
+		if (!(STM32_ADC_CR2(id) & (1 << 0))) {
+			/* Power on ADC module */
+			STM32_ADC_CR2(id) |= (1 << 0);  /* ADON */
+
+			/* Reset calibration */
+			STM32_ADC_CR2(id) |= (1 << 3);  /* RSTCAL */
+			while (STM32_ADC_CR2(id) & (1 << 3))
+				;
+
+			/* A/D Calibrate */
+			STM32_ADC_CR2(id) |= (1 << 2);  /* CAL */
+			while (STM32_ADC_CR2(id) & (1 << 2))
+				;
+		}
+
+		/* Set right alignment */
+		STM32_ADC_CR2(id) &= ~(1 << 11);
+
+		/* Set sampling time to 28.5 cycles */
+		STM32_ADC_SMPR2(id) = 0x3;
+
+		/* Select AIN0 */
+		STM32_ADC_SQR3(id) &= ~0x1f;
+
+		/* Disable DMA */
+		STM32_ADC_CR2(id) &= ~(1 << 8);
+
+		/* Disable scan mode */
+		STM32_ADC_CR1(id) &= ~(1 << 8);
+	}
+}
+
+static void timers_init(void)
+{
+	STM32_TIM_CR1(3) = 0x0004; /* MSB */
+	STM32_TIM_CR1(2) = 0x0004; /* LSB */
+
+	STM32_TIM_CR2(3) = 0x0000;
+	STM32_TIM_CR2(2) = 0x0020;
+
+	STM32_TIM_SMCR(3) = 0x0007 | (1 << 4);
+	STM32_TIM_SMCR(2) = 0x0000;
+
+	STM32_TIM_ARR(3) = 0xffff;
+	STM32_TIM_ARR(2) = 0xffff;
+
+	STM32_TIM_PSC(3) = 0;
+	STM32_TIM_PSC(2) = CPU_CLOCK / 1000000 - 1;
+
+	STM32_TIM_EGR(3) = 0x0001;
+	STM32_TIM_EGR(2) = 0x0001;
+
+	STM32_TIM_DIER(3) = 0x0001;
+	STM32_TIM_DIER(2) = 0x0000;
+
+	STM32_TIM_CR1(3) |= 1;
+	STM32_TIM_CR1(2) |= 1;
+
+	STM32_TIM_CNT(3) = 0;
+	STM32_TIM_CNT(2) = 0;
+
+	task_enable_irq(STM32_IRQ_TIM3);
+	task_enable_irq(STM32_IRQ_TIM2);
+}
+
+static void irq_init(void)
+{
+	/* clear all pending interrupts */
+	CPU_NVIC_UNPEND(0) = 0xffffffff;
+	/* enable global interrupts */
+	asm("cpsie i");
+}
+
+void hardware_init(void)
+{
+	power_init();
+	clock_init();
+	pins_init();
+	timers_init();
+	adc_init();
+	irq_init();
+}
diff --git a/board/keyborg/runtime.c b/board/keyborg/runtime.c
new file mode 100644
index 0000000000..89306d85fd
--- /dev/null
+++ b/board/keyborg/runtime.c
@@ -0,0 +1,118 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* tiny substitute of the runtime layer */
+
+#include "common.h"
+#include "cpu.h"
+#include "debug.h"
+#include "irq_handler.h"
+#include "registers.h"
+#include "timer.h"
+#include "util.h"
+
+volatile uint32_t last_event;
+
+static uint32_t last_deadline;
+static uint8_t need_wfi;
+
+timestamp_t get_time(void)
+{
+	timestamp_t t;
+	uint32_t hi, lo;
+
+	do {
+		hi = STM32_TIM_CNT(3);
+		lo = STM32_TIM_CNT(2);
+	} while (hi != STM32_TIM_CNT(3));
+
+	t.le.lo = (hi << 16) | lo;
+	t.le.hi = 0;
+
+	return t;
+}
+
+void udelay(unsigned us)
+{
+	unsigned t0 = get_time().le.lo;
+	while ((get_time().le.lo - t0) < us)
+		;
+}
+
+void task_enable_irq(int irq)
+{
+	CPU_NVIC_EN(0) = 1 << irq;
+}
+
+void task_disable_irq(int irq)
+{
+	CPU_NVIC_DIS(0) = 1 << irq;
+}
+
+void task_clear_pending_irq(int irq)
+{
+	CPU_NVIC_UNPEND(0) = 1 << irq;
+}
+
+uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
+{
+	last_event = event;
+
+	return 0;
+}
+
+void IRQ_HANDLER(STM32_IRQ_TIM2)(void)
+{
+	if (STM32_TIM_CNT(3) == last_deadline >> 16) {
+		STM32_TIM_DIER(2) = 0;
+		task_clear_pending_irq(STM32_IRQ_TIM2);
+		last_event = 1 << 29 /* task event wake */;
+		need_wfi = 0;
+	} else {
+		need_wfi = 1;
+	}
+}
+
+void __hw_clock_event_set(uint32_t deadline)
+{
+	last_deadline = deadline;
+	STM32_TIM_CCR1(2) = deadline & 0xffff;
+	STM32_TIM_SR(2) = ~2;
+	STM32_TIM_DIER(2) |= 2;
+}
+
+uint32_t task_wait_event(int timeout_us)
+{
+	uint32_t evt;
+
+	/* the event already happened */
+	if (last_event || !timeout_us) {
+		evt = last_event;
+		last_event = 0;
+
+		return evt;
+	}
+
+	/* set timeout on timer */
+	if (timeout_us > 0)
+		__hw_clock_event_set(get_time().le.lo + timeout_us);
+
+	do {
+		/* sleep until next interrupt */
+		asm volatile("wfi");
+
+		STM32_TIM_DIER(2) = 0; /* disable match interrupt */
+		evt = last_event;
+		last_event = 0;
+	} while (need_wfi);
+
+	return evt;
+}
+
+/* --- stubs --- */
+void __hw_timer_enable_clock(int n, int enable)
+{ /* Done in hardware init */ }
+
+void usleep(unsigned us)
+{ /* Used only as a workaround */ }
diff --git a/chip/stm32/clock-stm32f.c b/chip/stm32/clock-stm32f.c
index 21380c492a..ea438a04cd 100644
--- a/chip/stm32/clock-stm32f.c
+++ b/chip/stm32/clock-stm32f.c
@@ -128,6 +128,9 @@ DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
  */
 #define DESIRED_CPU_CLOCK 48000000
 #define RCC_CFGR 0x00680000
+#elif defined(BOARD_KEYBORG)
+#define DESIRED_CPU_CLOCK 48000000
+#define RCC_CFGR 0x00684000
 #else
 #error "Need board-specific clock settings"
 #endif
diff --git a/chip/stm32/config-stm32ts60.h b/chip/stm32/config-stm32ts60.h
new file mode 100644
index 0000000000..2e92016830
--- /dev/null
+++ b/chip/stm32/config-stm32ts60.h
@@ -0,0 +1,46 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_BASE       0x08000000
+#define CONFIG_FLASH_PHYSICAL_SIZE 0x0010000 /* Actually 0x8000 */
+#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
+#define CONFIG_FLASH_BANK_SIZE  0x1000  /* TODO */
+#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* TODO erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* TODO minimum write size */
+
+/* No page mode on STM32F, so no benefit to larger write sizes */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
+
+#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_SIZE         0x00002800
+
+/* Size of one firmware image in flash */
+#define CONFIG_FW_IMAGE_SIZE    (32 * 1024)
+
+#define CONFIG_FW_RO_OFF        0
+#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
+#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
+#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+
+/*
+ * Put pstate after RO to give RW more space and make RO write protect region
+ * contiguous.
+ */
+#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 59
+
+/* Reduced history because of limited RAM */
+#undef CONFIG_CONSOLE_HISTORY
+#define CONFIG_CONSOLE_HISTORY 3
+
+/* Only USART2 support */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 2
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index a01909045c..b2479f21b9 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -34,6 +34,9 @@
 #elif defined(CHIP_VARIANT_STM32F03X)
 /* STM32F03x */
 #include "config-stm32f03x.h"
+#elif defined(CHIP_VARIANT_STM32TS60)
+/* STM32TS60 */
+#include "config-stm32ts60.h"
 #else
 #error "Unsupported chip variant"
 #endif
diff --git a/chip/stm32/gpio-stm32f.c b/chip/stm32/gpio-stm32f.c
index e9f7944354..79fc2235d0 100644
--- a/chip/stm32/gpio-stm32f.c
+++ b/chip/stm32/gpio-stm32f.c
@@ -138,7 +138,11 @@ void gpio_pre_init(void)
 		 * TODO(crosbug.com/p/23770): only enable the banks we need to,
 		 * and support disabling some of them in low-power idle.
 		 */
+#ifdef CHIP_VARIANT_STM32TS60
+		STM32_RCC_APB2ENR |= 0x7fd;
+#else
 		STM32_RCC_APB2ENR |= 0x1fd;
+#endif
 	}
 
 	/* Set all GPIOs to defaults */
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index d3485824c8..dd4ceb13d6 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -46,6 +46,7 @@
 #define STM32_IRQ_USB             31
 /* aliases for easier code sharing */
 #define STM32_IRQ_COMP STM32_IRQ_ADC_COMP
+
 #else /* !CHIP_FAMILY_STM32F0 */
 #define STM32_IRQ_WWDG             0
 #define STM32_IRQ_PVD              1
@@ -65,7 +66,14 @@
 #define STM32_IRQ_DMA_CHANNEL_5   15
 #define STM32_IRQ_DMA_CHANNEL_6   16
 #define STM32_IRQ_DMA_CHANNEL_7   17
+#define STM32_IRQ_DMA_CHANNEL_8   18 /* STM32TS60 only */
+
+#ifdef CHIP_VARIANT_STM32TS60
+#define STM32_IRQ_ADC_1           21
+#else
 #define STM32_IRQ_ADC_1           18 /* ADC1 and ADC2 interrupt on STM32F10x */
+#endif
+
 #define STM32_IRQ_USB_HP          19
 #define STM32_IRQ_CAN_TX          19 /* STM32F10x only */
 #define STM32_IRQ_USB_LP          20
@@ -74,11 +82,14 @@
 #define STM32_IRQ_CAN_RX1         21 /* STM32F10x only */
 #define STM32_IRQ_COMP            22
 #define STM32_IRQ_CAN_SCE         22 /* STM32F10x only */
+#define STM32_IRQ_ADC_2           22 /* STM32TS60 only */
 #define STM32_IRQ_EXTI9_5         23
 #define STM32_IRQ_LCD             24 /* STM32L15X only */
 #define STM32_IRQ_TIM1_BRK_TIM15  24 /* TIM15 interrupt on STM32F100 only */
+#define STM32_IRQ_PMAD            24 /* STM32TS60 only */
 #define STM32_IRQ_TIM9            25 /* STM32L15X only */
 #define STM32_IRQ_TIM1_UP_TIM16   25 /* TIM16 interrupt on STM32F100 only */
+#define STM32_IRQ_PMSE            25 /* STM32TS60 only */
 #define STM32_IRQ_TIM10           26 /* STM32L15X only */
 #define STM32_IRQ_TIM1_TRG_TIM17  26 /* STM32F100 only */
 #define STM32_IRQ_TIM1_TRG_COM    26 /* STM32F10x only */
@@ -293,6 +304,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define GPIO_F                       STM32_GPIOF_BASE
 #define GPIO_G                       STM32_GPIOG_BASE
 #define GPIO_H                       STM32_GPIOH_BASE
+#define GPIO_I                       STM32_GPIOI_BASE
 
 #define DUMMY_GPIO_BANK GPIO_A
 
@@ -358,6 +370,8 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_GPIOE_BASE            0x40011800
 #define STM32_GPIOF_BASE            0x4001c000
 #define STM32_GPIOG_BASE            0x40012000
+#define STM32_GPIOH_BASE            0x40012400 /* STM32TS only */
+#define STM32_GPIOI_BASE            0x40012800 /* STM32TS only */
 
 #define STM32_GPIO_CRL(b)       REG32((b) + 0x00)
 #define STM32_GPIO_CRH(b)       REG32((b) + 0x04)
@@ -522,6 +536,8 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_RCC_PB2_TIM15		(1 << 16) /* STM32F0XX */
 #define STM32_RCC_PB2_TIM16		(1 << 17) /* STM32F0XX */
 #define STM32_RCC_PB2_TIM17		(1 << 18) /* STM32F0XX */
+#define STM32_RCC_PB2_PMAD		(1 << 11) /* STM32TS */
+#define STM32_RCC_PB2_PMSE		(1 << 13) /* STM32TS */
 #define STM32_RCC_PB1_TIM14		(1 << 8)  /* STM32F0XX */
 
 #define STM32_SYSCFG_BASE           0x40010000
@@ -667,7 +683,10 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI_CR1_LSBFIRST		(1 << 7)
 #define STM32_SPI_CR1_SPE		(1 << 6)
 #define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R		(1 << 3)
 #define STM32_SPI_CR1_MSTR		(1 << 2)
+#define STM32_SPI_CR2_RXNEIE		(1 << 6)
+#define STM32_SPI_CR2_SSOE		(1 << 2)
 #define STM32_SPI_CR2_RXDMAEN		(1 << 0)
 #define STM32_SPI_CR2_TXDMAEN		(1 << 1)
 #define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
@@ -763,10 +782,16 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 
 /* --- ADC --- */
 
+#if defined(CHIP_VARIANT_STM32TS60)
+#define STM32_ADC1_BASE             0x40013800
+#define STM32_ADC2_BASE             0x40013c00
+#define STM32_ADC_BASE(x)           (0x40013800 + 0x400 * (x))
+#else /* !CHIP_VARIANT_STM32TS60 */
 #define STM32_ADC1_BASE             0x40012400
 #define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
 #define STM32_ADC2_BASE             0x40012800 /* STM32F10x only */
 #define STM32_ADC3_BASE             0x40013C00 /* STM32F10x only */
+#endif
 
 #if defined(CHIP_VARIANT_STM32F100)
 #define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
@@ -784,6 +809,13 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
 #define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
 #define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
+#elif defined(CHIP_VARIANT_STM32TS60)
+#define STM32_ADC_SR(x)            REG32(STM32_ADC_BASE(x) + 0x00)
+#define STM32_ADC_CR1(x)           REG32(STM32_ADC_BASE(x) + 0x04)
+#define STM32_ADC_CR2(x)           REG32(STM32_ADC_BASE(x) + 0x08)
+#define STM32_ADC_SMPR2(x)         REG32(STM32_ADC_BASE(x) + 0x10)
+#define STM32_ADC_SQR3(x)          REG32(STM32_ADC_BASE(x) + 0x34)
+#define STM32_ADC_DR(x)            REG32(STM32_ADC_BASE(x) + 0x4c)
 #elif defined(CHIP_FAMILY_STM32F0)
 #define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
 #define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
@@ -1041,6 +1073,8 @@ enum dma_channel {
 	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
 	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
 	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
+	STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6,
+	STM32_DMAC_PMSE_COL = STM32_DMAC_CH7,
 
 	/* Only DMA1 (with 7 channels) is present on STM32F100 and STM32L151x */
 	STM32_DMAC_COUNT = 7,