diff options
| author | Caveh Jalali <caveh@chromium.org> | 2023-03-14 06:41:11 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-03-20 22:14:16 +0000 |
| commit | fff5dcdd4043f6f5d00cfb1862adcbdb34ccb343 (patch) | |
| tree | b46135734abfd977b374e947b53cd9b78a4e5143 | |
| parent | e2d115e2a8693d588df65178caea2a251662bbe3 (diff) | |
| download | chrome-ec-fff5dcdd4043f6f5d00cfb1862adcbdb34ccb343.tar.gz | |
npcx9: Move RW region so we can write protect RO region
The npcx9 internal flash write protect scheme is very limited. The
smallest protectable region is half of the entire flash device, so
allocate RO and RW regions to match the hardware.
Note: The EC image in the BIOS must match this new region allocation.
The only way to do this is to manually update the BIOS and EC. When the
BIOS triggers a software sync with mismatched region configurations, the
system will endlessly try to software sync.
BRANCH=none
BUG=b:260815079
TEST=FAFT firmware_ECCbiEeprom passes
Change-Id: Id5b9b2bc8d7858f3cb90ef39300ef1f654a080e6
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4334209
Reviewed-by: Keith Short <keithshort@chromium.org>
| -rw-r--r-- | zephyr/boards/arm/npcx9/npcx9m7f.dts | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/zephyr/boards/arm/npcx9/npcx9m7f.dts b/zephyr/boards/arm/npcx9/npcx9m7f.dts index df6c17c109..0083f2da6f 100644 --- a/zephyr/boards/arm/npcx9/npcx9m7f.dts +++ b/zephyr/boards/arm/npcx9/npcx9m7f.dts @@ -11,18 +11,23 @@ / { /* - * The NPCX9m7F includes 640 kB of code RAM, and 1 MB flash. Padding + * The NPCX9m7F includes 384 kB of code RAM, and 1 MB flash. Padding * is added to make the image the same size as the internal flash. This * is required to support the flashrom tool which requires an image that * matches the full internal flash size. */ binman { wp-ro { + /* + * wp-ro must match a block protect region supported by + * by the internal flash device. In practice, that's + * 512 KiB starting at address 0. + */ offset = <0x0>; - size = <0x50000>; + size = <0x80000>; }; ec-rw { - offset = <0x50000>; + offset = <0x80000>; size = <0x50000>; rw-fw { rw-fwid { @@ -37,6 +42,6 @@ }; }; pad-byte = <0xff>; - pad-after = <0x60000>; + pad-after = <0x30000>; }; }; |