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| author | Eric Yilun Lin <yllin@chromium.org> | 2023-03-17 16:22:06 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-03-20 10:08:10 +0000 |
| commit | 7a935e90ccc5e25732d740a683c4f68a0de70e26 (patch) | |
| tree | 833f7cb6bc7e2c7c0a6606152ecc7f065293b210 | |
| parent | 5c098877b2f7f8add7e134bcd82c07b8969d68fd (diff) | |
| download | chrome-ec-7a935e90ccc5e25732d740a683c4f68a0de70e26.tar.gz | |
mt8186: fix sysjump and hibernate actions
1. fix sysjump will boot the system with AP IDLE
1. fix boot with AP OFF
2. fix boot from hibernate
The recent change which make the system staying at S5 for 10 seconds
when AP power off. When sysjump requested, the RW part will
automatically boot the system from S5 due to the initial in_exiting_off
flag defaults to true. Since the exiting_off status is controlled by the
power_chipset_init, we don't need the flag defaults to true on boot.
Also, change the initial power state S5 to G3. They are the same in
rail-wise on mt8186, but not in mt8188. Assign it as G3 to match
mt8188 initial GPIO and rail states. When the AC on under hiberante,
or the EC boots with AP OFF flag, this ensures the system stay at G3.
BUG=b:274051287 b:274063396 b:274368558
TEST=pass firmware_ECPowerButton
TEST=pass firmware_ECWakeFromULP
TEST=dut-control cold_reset:on sleep:1 cold_reset:off, boot to S0
TEST=dut-control power_state:rec; dut-control power_key:tab. stay at
S5->G3
TEST=hibernate, and AC on. The EC stays at G3.
BRANCH=none
Change-Id: I253f4956665a6a0edc2fe59c5a8a90a7c07a6180
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4349381
Commit-Queue: Eric Yilun Lin <yllin@google.com>
Tested-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
| -rw-r--r-- | power/mt8186.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/power/mt8186.c b/power/mt8186.c index 9acb27dfa2..ad0f189510 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -88,7 +88,7 @@ static bool is_s5g3_passed; * indicate exiting off state, and don't respect the power signals until chipset * on. */ -static bool is_exiting_off = true; +static bool is_exiting_off; /* Turn on the PMIC power source to AP, this also boots AP. */ static void set_pmic_pwron(void) @@ -287,6 +287,14 @@ enum power_state power_chipset_init(void) return init_state; } + /* If the init signal state is at S5, assigns it to G3 to match the + * default GPIO and PP4200_S5 rail states. + */ + if (init_state == POWER_S5) { + init_state = POWER_G3; + is_s5g3_passed = true; + } + if (battery_is_present() == BP_YES) /* * (crosbug.com/p/28289): Wait battery stable. @@ -295,14 +303,9 @@ enum power_state power_chipset_init(void) */ battery_wait_for_stable(); - if (exit_hard_off) { - if (init_state == POWER_S5 || init_state == POWER_G3) { - /* Auto-power on */ - mt8186_exit_off(); - } else { - is_exiting_off = false; - } - } + if (exit_hard_off && init_state == POWER_G3) + /* Auto-power on */ + mt8186_exit_off(); if (init_state != POWER_G3 && !exit_hard_off) /* Force shutdown from S5 if the PMIC is already up. */ |