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| author | CHLin <CHLIN56@nuvoton.com> | 2018-08-24 15:58:49 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-08-26 22:52:28 -0700 |
| commit | 90bd02480e50f8c4a5d8f45fa0f894c02e85c0a1 (patch) | |
| tree | 825b47670aebfa11f1c972e6938adad792e90dbd | |
| parent | a3f0cc0830ebbe1015d47e7d9ce9109325289e8b (diff) | |
| download | chrome-ec-90bd02480e50f8c4a5d8f45fa0f894c02e85c0a1.tar.gz | |
npcx: don't clear DEVCNT_F_SPI_TRIS bit for chips that use intenal flash
As documented in the datasheet, NPCX_DEVCNT_F_SPI_TRIS must be 1 for ECs
that use internal flash (e.g., NPCX79nF and NPCX797W).
BRANCH=none
BUG=b:112906111
TEST=No build errors for make buildall. Flash image on npcx7_evb; check
this bit is not cleared. Flash image on yorp; check the platform boots
up to OS screen.
Change-Id: I533553ad91ce0ecc79fc55b86aa83bbbcf514d89
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1188180
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
| -rw-r--r-- | chip/npcx/flash.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index a3d62041b8..2106e68f75 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -690,7 +690,7 @@ int flash_pre_init(void) flash_pinmux(1); #endif -#ifdef CONFIG_EXTERNAL_STORAGE +#if defined(CONFIG_EXTERNAL_STORAGE) && !defined(NPCX_INT_FLASH_SUPPORT) /* Disable tristate all the time */ CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS); #endif |