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authorjames_chao <james_chao@asus.com>2015-12-03 23:26:43 +0800
committerChromeOS bot <3su6n15k.default@developer.gserviceaccount.com>2015-12-04 02:25:23 +0000
commit173e17ae00073eef7aa2e7b082ad89d48888677e (patch)
tree794db512f335b6e404af6c25ce70a1b957077320
parente6382ca48437ba714215f999e776c6c0a5c1dd14 (diff)
downloadchrome-ec-173e17ae00073eef7aa2e7b082ad89d48888677e.tar.gz
Terra: add IMAGE_SEL gpio
There are terra12 and terra13, use gpio IMAGE_SEL to identify. IMAGE_SEL is low for terra12, IMAGE_SEL is high for terra13. BUG=None BRANCH=firmware-strago-7287.B TEST=None Change-Id: I874905337aea97de70db1fb058b05625d5c1d026 Signed-off-by: james_chao <james_chao@asus.com> Reviewed-on: https://chromium-review.googlesource.com/315432 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
-rw-r--r--board/terra/gpio.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/board/terra/gpio.inc b/board/terra/gpio.inc
index 91734d9f99..6241e962e3 100644
--- a/board/terra/gpio.inc
+++ b/board/terra/gpio.inc
@@ -83,6 +83,7 @@ GPIO(PCH_PWRBTN_L, PIN(160), GPIO_OUT_HIGH) /* Power button
GPIO(STARTUP_LATCH_SET, PIN(201), GPIO_INPUT) /* Not used in BCRD2. Programmed as Input to fix EC power leakage in S3*/
GPIO(EC_BL_DISABLE_L, PIN(202), GPIO_OUT_HIGH) /* EDP backligh disable signal from EC */
GPIO(SMC_SHUTDOWN, PIN(203), GPIO_OUT_LOW) /* Shutdown signal from EC to power sequencing PLD */
+GPIO(IMAGE_SEL, PIN(204), GPIO_INPUT)
GPIO(BAT_PRESENT_L, PIN(210), GPIO_INPUT) /* HW detection signal from battery to EC */
GPIO(GPIO_3_EC, PIN(211), GPIO_OUT_LOW) /* Sleep SOIX signal from SOC to EC */