diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2021-11-09 17:22:43 -0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-28 18:17:21 +0000 |
| commit | 8fee5eff7ed8bb22b8c0f9337b2f7ea373de7cc7 (patch) | |
| tree | f6687312895912036dd90b6a024ff860c534ab09 | |
| parent | 930f0fb171a189e83ac581181d2fa211b3c7338c (diff) | |
| download | chrome-ec-8fee5eff7ed8bb22b8c0f9337b2f7ea373de7cc7.tar.gz | |
ectool/panicinfo: Print extra cortex-m fault registers
This patch makes ectool panicinfo print extra cortex-m fault
registers, including CFSR, HFSR, and IPSR.
Saved panic data:
=== PROCESS EXCEPTION: ad ====== xPSR: ffffffff ===
r0 : r1 : r2 : r3 :
r4 :dead6664 r5 :100995ae r6 :00000000 r7 :00000000
r8 :00000000 r9 :00000000 r10:00000000 r11:00000000
r12: sp :00000000 lr : pc :
cfsr=00000000, shcsr=000000000, hfsr=10000028, dfsr=00000000, ipsr=100995ad
BUG=b:218982018,b:200593658
BRANCH=None
TEST=Run on Nami. See a sample output above.
Change-Id: I56ecbefa2414553ab2204f113bedcad67b5ccad6
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3271886
Reviewed-by: caveh jalali <caveh@chromium.org>
(cherry picked from commit 0819d1e49b3dbc2416610e005af090249860673c)
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3456703
| -rw-r--r-- | util/ec_panicinfo.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/util/ec_panicinfo.c b/util/ec_panicinfo.c index 47de4b2a4c..296774021f 100644 --- a/util/ec_panicinfo.c +++ b/util/ec_panicinfo.c @@ -23,6 +23,26 @@ static void print_panic_reg(int regnum, const uint32_t *regs, int index) printf((regnum & 3) == 3 ? "\n" : " "); } +static void panic_show_extra_cm(const struct panic_data *pdata) +{ + enum { + CPU_NVIC_CFSR_BFARVALID = 1 << 15, + CPU_NVIC_CFSR_MFARVALID = 1 << 7, + }; + + printf("\n"); + if (pdata->cm.cfsr & CPU_NVIC_CFSR_BFARVALID) + printf("bfar=%08x, ", pdata->cm.bfar); + if (pdata->cm.cfsr & CPU_NVIC_CFSR_MFARVALID) + printf("mfar=%08x, ", pdata->cm.mfar); + printf("cfsr=%08x, ", pdata->cm.cfsr); + printf("shcsr=%08x, ", pdata->cm.shcsr); + printf("hfsr=%08x, ", pdata->cm.hfsr); + printf("dfsr=%08x, ", pdata->cm.dfsr); + printf("ipsr=%08x", pdata->cm.regs[CORTEX_PANIC_REGISTER_IPSR]); + printf("\n"); +} + static int parse_panic_info_cm(const struct panic_data *pdata) { const uint32_t *lregs = pdata->cm.regs; @@ -65,6 +85,8 @@ static int parse_panic_info_cm(const struct panic_data *pdata) print_panic_reg(14, sregs, 5); print_panic_reg(15, sregs, 6); + panic_show_extra_cm(pdata); + return 0; } |