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| author | Daisuke Nojiri <dnojiri@chromium.org> | 2021-10-11 12:50:25 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-28 21:12:56 +0000 |
| commit | 2b081d0e6e346085318be2118cccd865c1da0f8d (patch) | |
| tree | 1e0d1bdc7490cb6eec0e407c2d71ffad37d511d5 | |
| parent | 768322d728e8e9228b8ce46dfbf0c8954b8650c4 (diff) | |
| download | chrome-ec-2b081d0e6e346085318be2118cccd865c1da0f8d.tar.gz | |
watchdog: Save LR in panic data when watchdog triggers
We currently save a panic reason (e.g. PANIC_SW_WATCHDOG), PC, task
index but not LR. LR often points to the actual code causing the crash
because PC points to a generic API (e.g. udelay).
This patch makes the watchdog handler store LR to cm.hfsr. It is for
HardFault status register but it is probably the least informative
register used by chip_panic_data_backup/restore of the existing RO.
BUG=b:200593658
BRANCH=Nami
TEST=Sona. Run crash watchdog. Verify panic_data_print prints LR.
Change-Id: Icf9fffe1a8eed0d3b7e8d36f9c6234fe56133ea4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3218118
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457945
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Ricardo Quesada <ricardoq@chromium.org>
Tested-by: Ricardo Quesada <ricardoq@chromium.org>
Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
| -rw-r--r-- | core/cortex-m/watchdog.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/core/cortex-m/watchdog.c b/core/cortex-m/watchdog.c index a67903df62..4da32d26d0 100644 --- a/core/cortex-m/watchdog.c +++ b/core/cortex-m/watchdog.c @@ -7,10 +7,14 @@ #include "common.h" #include "panic.h" +#include "system.h" #include "task.h" #include "timer.h" #include "watchdog.h" +/* Panic data goes at the end of RAM. */ +static struct panic_data * const pdata_ptr = PANIC_DATA_PTR; + void __keep watchdog_trace(uint32_t excep_lr, uint32_t excep_sp) { uint32_t psp; @@ -28,6 +32,13 @@ void __keep watchdog_trace(uint32_t excep_lr, uint32_t excep_sp) panic_set_reason(PANIC_SW_WATCHDOG, stack[6], (excep_lr & 0xf) == 1 ? 0xff : task_get_current()); + /* + * Store LR to cm.hfsr. It is for HardFault status register but it is + * probably the least informative register used by + * chip_panic_data_backup of the existing RO. + */ + pdata_ptr->cm.hfsr = stack[5]; + panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ", stack[6], stack[5], psp); if ((excep_lr & 0xf) == 1) |