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authorJett Rink <jettrink@chromium.org>2018-03-22 10:18:49 -0600
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2018-03-27 18:22:57 +0000
commite1f2136d8af819af173fc1288877f938ca7f13c2 (patch)
treed473368697152348c15a14c555b17de199ba85b2
parenta245cd67bb68f9bc5e25883c29e37d6cf537be9b (diff)
downloadchrome-ec-e1f2136d8af819af173fc1288877f938ca7f13c2.tar.gz
lpc: remove lpc_host_reset
No one is using this method and it implies that all chipset should support the RCIN# Virtual Wire if using eSPI. Only large core chips use RCIN#; small core chips don't. This method was introduced for skylake and has since been replaced since CL:575947 was merged. BRANCH=none BUG=none TEST=build all Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/975904 Reviewed-on: https://chromium-review.googlesource.com/982347 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
-rw-r--r--chip/it83xx/lpc.c14
-rw-r--r--chip/mchp/lpc.c18
-rw-r--r--chip/npcx/lpc.c27
-rw-r--r--include/lpc.h5
4 files changed, 0 insertions, 64 deletions
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 231dd25ece..bde0ebf0c1 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -703,20 +703,6 @@ static void lpc_init(void)
*/
DECLARE_HOOK(HOOK_INIT, lpc_init, HOOK_PRIO_INIT_LPC);
-void lpc_host_reset(void)
-{
- /* Host Reset Control will assert RCIN# */
-#ifdef CONFIG_ESPI_VW_SIGNALS
- espi_vw_set_wire(VW_RCIN_L, 0);
- udelay(10);
- espi_vw_set_wire(VW_RCIN_L, 1);
-#else
- gpio_set_level(GPIO_SYS_RESET_L, 0);
- udelay(10);
- gpio_set_level(GPIO_SYS_RESET_L, 1);
-#endif
-}
-
#ifndef CONFIG_ESPI_VW_SIGNALS
void lpcrst_interrupt(enum gpio_signal signal)
{
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
index 37c2adc6ac..ac47b042f6 100644
--- a/chip/mchp/lpc.c
+++ b/chip/mchp/lpc.c
@@ -466,24 +466,6 @@ DECLARE_DEFERRED(lpc_chipset_reset);
#endif
-#ifdef CONFIG_ESPI
-/*
- * Called from power/skylake.c chipset_reset()
- * For LPC it doesn't call here, instead it pulses RCIN# low for 10 us
- */
-void lpc_host_reset(void)
-{
- /* Host Reset Control will assert KBRST# (LPC) or RCIN# VW (eSPI) */
-#ifdef CONFIG_ESPI_VW_SIGNALS
- espi_vw_pulse_wire(VW_RCIN_L, 0);
-#else
- gpio_set_level(GPIO_PCH_RCIN_L, 0);
- udelay(10);
- gpio_set_level(GPIO_PCH_RCIN_L, 1);
-#endif
-}
-#endif /* #ifdef CONFIG_ESPI */
-
void lpc_set_init_done(int val)
{
init_done = val;
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 078474b2e5..518e15f957 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -792,33 +792,6 @@ int lpc_get_pltrst_asserted(void)
return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT);
}
-void lpc_host_reset(void)
-{
- /* Host Reset Control will assert KBRST# (LPC) or RCIN# VW (eSPI) */
-#ifdef CONFIG_ESPI_VW_SIGNALS
- int timeout = 100; /* 100 * 10us = 1ms */
-
- /* Assert RCIN# VW to host */
- SET_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB);
-
- /* Poll for dirty bit to clear to indicate VW read by host */
- while ((NPCX_VWEVSM(2) & VWEVSM_DIRTY(1))) {
- if (!timeout--) {
- CPRINTS("RCIN# VW Timeout");
- break;
- }
- udelay(10);
- }
-
- /* Deassert RCIN# VW to host */
- CLEAR_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB);
-#else
- SET_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB);
- udelay(10);
- CLEAR_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB);
-#endif
-}
-
#ifndef CONFIG_ESPI
/* Initialize host settings by interrupt */
void lpc_lreset_pltrst_handler(void)
diff --git a/include/lpc.h b/include/lpc.h
index c95999a98e..4f00d2cc3a 100644
--- a/include/lpc.h
+++ b/include/lpc.h
@@ -125,11 +125,6 @@ void lpc_clear_acpi_status_mask(uint8_t mask);
*/
int lpc_get_pltrst_asserted(void);
-/**
- * Reset the host with KBRST# or RCIN#
- */
-void lpc_host_reset(void);
-
/* Disable LPC ACPI interrupts */
void lpc_disable_acpi_interrupts(void);