chip/npcx: Ensure software watchdog has highest priority

Before this change uart_ec_interrupt and software watchdog
interrupt handler both had priority 0. Since UART IRQ number is
33, and software watchdog is 44, the UART interrupt handler
would have higher prority.

Fix this by increasing all interrupt handler priorities, leaving
the software watchdog handler alone on priority 0.

BRANCH=eve,poppy,fizz
BUG=b:76391320
TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt
     handler), check that panicinfo contains a sensible PC in r5
     after reset.

Change-Id: I8275e0a4c1a5307139fb6be0387eb5787b1209d4
Original-Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e
Original-Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/979738
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1029251
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>

11 files changed, 40 insertions, 40 deletions

diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c
index 6829a627a0..1712b889ab 100644
--- a/chip/npcx/adc.c
+++ b/chip/npcx/adc.c
@@ -161,7 +161,7 @@ void adc_interrupt(void)
 			task_set_event(task_waiting, TASK_EVENT_ADC_DONE, 0);
 	}
 }
-DECLARE_IRQ(NPCX_IRQ_ADC, adc_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_ADC, adc_interrupt, 4);
 
 /**
  * ADC initial.
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
index 6fc3e2b919..21766701a0 100644
--- a/chip/npcx/espi.c
+++ b/chip/npcx/espi.c
@@ -503,7 +503,7 @@ void __espi_wk2a_interrupt(void)
 	if (IS_BIT_SET(pending_bits, 6))
 		espi_vw_evt_oobrst();
 }
-DECLARE_IRQ(NPCX_IRQ_WKINTA_2, __espi_wk2a_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_2, __espi_wk2a_interrupt, 3);
 
 /* Handle eSPI virtual wire interrupt 2 */
 void __espi_wk2b_interrupt(void)
@@ -519,7 +519,7 @@ void __espi_wk2b_interrupt(void)
 	if (IS_BIT_SET(pending_bits, 0))
 		espi_vw_evt_hostrst_warn();
 }
-DECLARE_IRQ(NPCX_IRQ_WKINTB_2, __espi_wk2b_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_2, __espi_wk2b_interrupt, 3);
 
 /* Interrupt handler for eSPI status changed */
 void espi_interrupt(void)
@@ -595,7 +595,7 @@ void espi_interrupt(void)
 		status = NPCX_ESPISTS & mask;
 	}
 }
-DECLARE_IRQ(NPCX_IRQ_ESPI, espi_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_ESPI, espi_interrupt, 4);
 
 /*****************************************************************************/
 /* eSPI Initialization functions */
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index d19e6c2107..c0fd7cc35f 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -582,31 +582,31 @@ GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
 GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
 #endif
 
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 2);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 2);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 2);
-DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 2);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 2);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 3);
 #ifndef HAS_TASK_KEYSCAN
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 2);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 3);
 #ifdef CONFIG_HOSTCMD_SPS
 /*
- * HACK: Make CS GPIO P1 to improve SHI reliability.
+ * HACK: Make CS GPIO P2 to improve SHI reliability.
  * TODO: Increase CS-assertion-to-transaction-start delay on host to
- * accommodate P2 CS interrupt.
+ * accommodate P3 CS interrupt.
  */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 1);
-#else
 DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 2);
+#else
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 2);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 3);
 #if defined(CHIP_FAMILY_NPCX7)
-DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 3);
 #endif
 
 #undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c
index 8d92990048..e46a56fb1e 100644
--- a/chip/npcx/hwtimer.c
+++ b/chip/npcx/hwtimer.c
@@ -196,7 +196,7 @@ void __hw_clock_event_irq(void)
 #endif
 
 }
-DECLARE_IRQ(ITIM16_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 2);
+DECLARE_IRQ(ITIM16_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 3);
 
 
 /*****************************************************************************/
@@ -265,7 +265,7 @@ void __hw_clock_source_irq(void)
 #endif
 	}
 }
-DECLARE_IRQ(NPCX_IRQ_ITIM32, __hw_clock_source_irq, 2);
+DECLARE_IRQ(NPCX_IRQ_ITIM32, __hw_clock_source_irq, 3);
 
 /* Handle ITIM32 overflow if interrupt is disabled */
 void __hw_clock_handle_overflow(uint32_t clksrc_high)
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
index cb8e749640..926a5a26c5 100644
--- a/chip/npcx/i2c.c
+++ b/chip/npcx/i2c.c
@@ -581,15 +581,15 @@ void i2c6_interrupt(void) { handle_interrupt(6); }
 void i2c7_interrupt(void) { handle_interrupt(7); }
 #endif
 
-DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_SMB2, i2c1_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_SMB3, i2c2_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_SMB4, i2c3_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4);
+DECLARE_IRQ(NPCX_IRQ_SMB2, i2c1_interrupt, 4);
+DECLARE_IRQ(NPCX_IRQ_SMB3, i2c2_interrupt, 4);
+DECLARE_IRQ(NPCX_IRQ_SMB4, i2c3_interrupt, 4);
 #if defined(CHIP_FAMILY_NPCX7)
-DECLARE_IRQ(NPCX_IRQ_SMB5, i2c4_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_SMB6, i2c5_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_SMB7, i2c6_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_SMB8, i2c7_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_SMB5, i2c4_interrupt, 4);
+DECLARE_IRQ(NPCX_IRQ_SMB6, i2c5_interrupt, 4);
+DECLARE_IRQ(NPCX_IRQ_SMB7, i2c6_interrupt, 4);
+DECLARE_IRQ(NPCX_IRQ_SMB8, i2c7_interrupt, 4);
 #endif
 
 /*****************************************************************************/
diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c
index fa003c4336..96390a5720 100644
--- a/chip/npcx/keyboard_raw.c
+++ b/chip/npcx/keyboard_raw.c
@@ -154,7 +154,7 @@ void keyboard_raw_interrupt(void)
 	/* Wake the scan task */
 	task_wake(TASK_ID_KEYSCAN);
 }
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, keyboard_raw_interrupt, 4);
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, keyboard_raw_interrupt, 5);
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 0f2c295d4a..d37c47ed1c 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -588,7 +588,7 @@ void lpc_kbc_ibf_interrupt(void)
 	CPRINTS("ibf isr %02x", NPCX_HIKMDI);
 	task_wake(TASK_ID_KEYPROTO);
 }
-DECLARE_IRQ(NPCX_IRQ_KBC_IBF, lpc_kbc_ibf_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_KBC_IBF, lpc_kbc_ibf_interrupt, 4);
 
 /* KB controller output buffer empty ISR */
 void lpc_kbc_obe_interrupt(void)
@@ -600,7 +600,7 @@ void lpc_kbc_obe_interrupt(void)
 	CPRINTS("obe isr %02x", NPCX_HIKMST);
 	task_wake(TASK_ID_KEYPROTO);
 }
-DECLARE_IRQ(NPCX_IRQ_KBC_OBE, lpc_kbc_obe_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_KBC_OBE, lpc_kbc_obe_interrupt, 4);
 #endif
 
 /* PM channel input buffer full ISR */
@@ -614,13 +614,13 @@ void lpc_pmc_ibf_interrupt(void)
 	else if (NPCX_HIPMST(PMC_HOST_CMD) & 0x02)
 		handle_host_write((NPCX_HIPMST(PMC_HOST_CMD)&0x08) ? 1 : 0);
 }
-DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4);
 
 /* PM channel output buffer empty ISR */
 void lpc_pmc_obe_interrupt(void)
 {
 }
-DECLARE_IRQ(NPCX_IRQ_PM_CHAN_OBE, lpc_pmc_obe_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_PM_CHAN_OBE, lpc_pmc_obe_interrupt, 4);
 
 void lpc_port80_interrupt(void)
 {
@@ -637,7 +637,7 @@ void lpc_port80_interrupt(void)
 	/* Clear pending bit of host writing */
 	SET_BIT(NPCX_DP80STS, 5);
 }
-DECLARE_IRQ(NPCX_IRQ_PORT80, lpc_port80_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_PORT80, lpc_port80_interrupt, 4);
 
 /**
  * Preserve event masks across a sysjump.
diff --git a/chip/npcx/peci.c b/chip/npcx/peci.c
index 0d109adda6..3d8d1fe154 100644
--- a/chip/npcx/peci.c
+++ b/chip/npcx/peci.c
@@ -278,7 +278,7 @@ void peci_done_interrupt(void){
 	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_CRC_ERR);
 	SET_BIT(NPCX_PECI_CTL_STS, NPCX_PECI_CTL_STS_ABRT_ERR);
 }
-DECLARE_IRQ(NPCX_IRQ_PECI, peci_done_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_PECI, peci_done_interrupt, 4);
 
 /*****************************************************************************/
 /* Console commands */
diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c
index b21482ccb9..1c0f1cb38a 100644
--- a/chip/npcx/shi.c
+++ b/chip/npcx/shi.c
@@ -827,7 +827,7 @@ void shi_int_handler(void)
 			log_unexpected_state("IBF");
 	}
 }
-DECLARE_IRQ(NPCX_IRQ_SHI, shi_int_handler, 1);
+DECLARE_IRQ(NPCX_IRQ_SHI, shi_int_handler, 2);
 
 /* Handle an CS assert event on the SHI_CS_L pin */
 void shi_cs_event(enum gpio_signal signal)
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c
index 066c19b34a..aa719ad640 100644
--- a/chip/npcx/uart.c
+++ b/chip/npcx/uart.c
@@ -234,7 +234,7 @@ void uart_ec_interrupt(void)
 	uart_process_input();
 	uart_process_output();
 }
-DECLARE_IRQ(NPCX_IRQ_UART, uart_ec_interrupt, 0);
+DECLARE_IRQ(NPCX_IRQ_UART, uart_ec_interrupt, 1);
 
 #ifdef CONFIG_UART_PAD_SWITCH
 /*
diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
index a8631ac893..5892f490a8 100644
--- a/chip/npcx/wov.c
+++ b/chip/npcx/wov.c
@@ -581,7 +581,7 @@ void wov_interrupt_handler(void)
 	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, wov_status);
 }
 
-DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 3);
+DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 4);
 
 /**
  * Enable FMUL2.