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| author | Dino Li <Dino.Li@ite.com.tw> | 2022-10-17 17:05:41 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-10-18 18:15:57 +0000 |
| commit | a5ea0d03b81ae933316f46b8a81a7aac9b234642 (patch) | |
| tree | d8a8b612af672ce579187766a4f4d61a5842741c | |
| parent | ea13c79313f0ce27d62cf369d5a0b6bff8539cd3 (diff) | |
| download | chrome-ec-a5ea0d03b81ae933316f46b8a81a7aac9b234642.tar.gz | |
it83xx: espi: reset pltrst# virtual wire signal during espi reset
EC software reset doesn't reset pltrst# by default.
This change was made to reset pltrst# during espi reset.
So Ampton won't get stuck after watchdog reset.
BRANCH=octopus
BUG=b:235443631,b:231246484
TEST=Ampton won't get stuck after watchdog reset.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ice77a902185046757d6b7bc70edee53eb81e64dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3959261
Commit-Queue: Henry Sun <henrysun@google.com>
Reviewed-by: luluboy luluboys <luluboy5208@gmail.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Tested-by: Luluboy Jian <luluboy_jian@asus.corp-partner.google.com>
Tested-by: luluboy luluboys <luluboy5208@gmail.com>
Reviewed-by: Luluboy Jian <luluboy_jian@asus.corp-partner.google.com>
(cherry picked from commit e82fb744a9596e411d568926e27640c4494f547e)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3960652
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: James Chao <james_chao@asus.corp-partner.google.com>
Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com>
| -rw-r--r-- | chip/it83xx/clock.c | 3 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 75c4e1dbeb..16f8a1c621 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -268,7 +268,10 @@ void clock_init(void) * version, so we have to reset eSPI configurations during init to * ensure Host and EC are synchronized (especially for the field of * I/O mode) + * Since bit4 of VWCTRL2 register is enabled, the below reset routine + * will be able to reset pltrst# signal. */ + IT83XX_ESPI_VWCTRL2 |= ESPI_PLTRST_ESPI_RESET; if (!system_jumped_to_this_image()) espi_fw_reset_module(); #endif diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index ddb2bbefbe..58014788a5 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1337,6 +1337,8 @@ enum usbpd_port { #define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE+0x91) #define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE+0x92) #define IT83XX_ESPI_VWCTRL3 REG8(IT83XX_ESPI_VW_BASE+0x93) +/* 1b: Refers to espi_reset# for pltrst */ +#define ESPI_PLTRST_ESPI_RESET BIT(4) /* eSPI Queue 0 */ #define IT83XX_ESPI_QUEUE_BASE 0x00F03300 |