diff options
author | JuHyun Kim <jkim@invensense.com> | 2022-01-20 00:24:36 -0800 |
---|---|---|
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-05-01 00:28:57 +0000 |
commit | 97e905010494285eceb012970e147910dfcd5011 (patch) | |
tree | cd983acc37e2c225bcadb0c1e8524b66440c4479 | |
parent | 5719ae1a67221a096eaf0fd290b1173599c31b98 (diff) | |
download | chrome-ec-97e905010494285eceb012970e147910dfcd5011.tar.gz |
driver: icm42607: removed SW reset and added POC initialize
Removed SW reset in initialize code due to hardware issue of ICM42607
Added registers initialization code instead of SW reset
BUG=chromium:1288737
BRANCH=None
TEST=ectool motionsense && CROS-EC IIO drivers
Signed-off-by: JuHyun Kim <jkim@invensense.com>
Change-Id: If14c071b82b62a7432cb1855cdf5d1c9dc744a91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3403824
Tested-by: JuHyun Kim <jkim@invensense.com>
Reviewed-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 86f19b3430623dab7ce8089a7d3564a98705c5ac)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3587802
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
-rw-r--r-- | driver/accelgyro_icm42607.c | 137 | ||||
-rw-r--r-- | driver/accelgyro_icm42607.h | 16 |
2 files changed, 133 insertions, 20 deletions
diff --git a/driver/accelgyro_icm42607.c b/driver/accelgyro_icm42607.c index b840ba3363..33ef71dd81 100644 --- a/driver/accelgyro_icm42607.c +++ b/driver/accelgyro_icm42607.c @@ -994,6 +994,123 @@ static int icm42607_init_config(const struct motion_sensor_t *s) /* Wait for 280 us for the OTP to load */ usleep(280); + /* Write POR value for all registers not loaded with OTP */ + ret = icm_write8(s, ICM42607_REG_GYRO_CONFIG0, 0x06); + if (ret) + return ret; + + ret = icm_write8(s, ICM42607_REG_ACCEL_CONFIG0, 0x06); + if (ret) + return ret; + + ret = icm_write8(s, ICM42607_REG_APEX_CONFIG0, 0x08); + if (ret) + return ret; + + ret = icm_write8(s, ICM42607_REG_APEX_CONFIG1, 0x02); + if (ret) + return ret; + + ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG1, 0x01); + if (ret) + return ret; + + ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG2, 0x00); + if (ret) + return ret; + + ret = icm_write8(s, ICM42607_REG_FIFO_CONFIG3, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_FIFO_CONFIG5, 0x20); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE7, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE8, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE9, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_INT_SOURCE10, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG2, 0xA2); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG3, 0x85); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG4, 0x51); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG5, 0x80); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG9, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG10, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG11, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER0, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER1, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER2, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER3, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER4, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER5, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER6, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER7, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_OFFSET_USER8, 0x00); + if (ret) + return ret; + + ret = icm_write_mclk_reg(s, ICM42607_MREG_APEX_CONFIG12, 0x00); + if (ret) + return ret; + ret = icm_switch_off_mclk(s); if (ret) return ret; @@ -1049,26 +1166,6 @@ static int icm42607_init(const struct motion_sensor_t *s) if (ret) goto out_unlock; - /* Reset to make sure previous state are not there */ - ret = icm_write8(s, ICM42607_REG_SIGNAL_PATH_RESET, - ICM42607_SOFT_RESET_DEV_CONFIG); - if (ret) - goto out_unlock; - - /* Check reset is done, 1ms max */ - for (i = 0; i < 5; ++i) { - usleep(200); - ret = icm_read8(s, ICM42607_REG_INT_STATUS, &val); - if (ret) - goto out_unlock; - if (val == ICM42607_RESET_DONE_INT) - break; - } - if (val != ICM42607_RESET_DONE_INT) { - ret = EC_ERROR_HW_INTERNAL; - goto out_unlock; - } - /* configure sensor */ ret = icm42607_init_config(s); if (ret) diff --git a/driver/accelgyro_icm42607.h b/driver/accelgyro_icm42607.h index f31392bf92..ccfd1e1d97 100644 --- a/driver/accelgyro_icm42607.h +++ b/driver/accelgyro_icm42607.h @@ -180,6 +180,8 @@ enum icm42607_ui_filt_bw { #define ICM42607_UI_FILT_BW_SET(_filt) ((_filt) & 0x07) #define ICM42607_REG_FIFO_CONFIG1 0x0028 +#define ICM42607_REG_FIFO_CONFIG2 0x0029 +#define ICM42607_REG_FIFO_CONFIG3 0x002A #define ICM42607_FIFO_STOP_ON_FULL_MODE BIT(1) #define ICM42607_FIFO_BYPASS BIT(0) #define ICM42607_FIFO_MODE_STREAM 0x00 @@ -258,6 +260,20 @@ enum icm42607_ui_filt_bw { #define ICM42607_OTP_COPY_TRIM (0x01 << 2) #define ICM42607_OTP_COPY_ST_DATA (0x03 << 2) +#define ICM42607_MREG_INT_SOURCE7 0x0030 +#define ICM42607_MREG_INT_SOURCE8 0x0031 +#define ICM42607_MREG_INT_SOURCE9 0x0032 +#define ICM42607_MREG_INT_SOURCE10 0x0033 + +#define ICM42607_MREG_APEX_CONFIG2 0x0044 +#define ICM42607_MREG_APEX_CONFIG3 0x0045 +#define ICM42607_MREG_APEX_CONFIG4 0x0046 +#define ICM42607_MREG_APEX_CONFIG5 0x0047 +#define ICM42607_MREG_APEX_CONFIG9 0x0048 +#define ICM42607_MREG_APEX_CONFIG10 0x0049 +#define ICM42607_MREG_APEX_CONFIG11 0x004A +#define ICM42607_MREG_APEX_CONFIG12 0x0067 + #define ICM42607_MREG_OFFSET_USER0 0x004E #define ICM42607_MREG_OFFSET_USER1 0x004F #define ICM42607_MREG_OFFSET_USER2 0x0050 |