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authorJett Rink <jettrink@chromium.org>2019-08-12 14:01:11 -0600
committerCommit Bot <commit-bot@chromium.org>2019-08-13 20:15:40 +0000
commit185455ac25228c8349fe4b3e22df791172a3e89a (patch)
tree5e1a0b7db26353dc9b9534859caa0ac465c8b5cb
parent3bd9b1115bee6c53a8010a5016342647d4d37512 (diff)
downloadchrome-ec-185455ac25228c8349fe4b3e22df791172a3e89a.tar.gz
ppc: initialize vbus current limit on init
The nx20p348 should also set the initial current limit during its initialization. BRANCH=octopus BUG=b:139110010,b:139201733 TEST=with CL stack, phaser limits both ports to 1.5A Change-Id: I876b32434bd37bf410d546a3d27f0f7ba949d3ea Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1752705
-rw-r--r--driver/ppc/nx20p348x.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c
index 35202c8fe8..4aa6700509 100644
--- a/driver/ppc/nx20p348x.c
+++ b/driver/ppc/nx20p348x.c
@@ -220,6 +220,7 @@ static int nx20p348x_init(int port)
int mask;
int mode;
int rv;
+ enum tcpc_rp_value initial_current_limit;
/* Mask interrupts for interrupt 2 register */
mask = ~NX20P348X_INT2_EN_ERR;
@@ -276,6 +277,14 @@ static int nx20p348x_init(int port)
*/
nx20p348x_set_ovp_limit(port);
+ /* Set the Vbus current limit after dead battery mode exit */
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+ initial_current_limit = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
+#else
+ initial_current_limit = TYPEC_RP_1A5;
+#endif
+ nx20p348x_set_vbus_source_current_limit(port, initial_current_limit);
+
return EC_SUCCESS;
}