diff options
author | Daisuke Nojiri <dnojiri@chromium.org> | 2019-03-06 02:45:27 +0000 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2019-03-06 17:58:14 +0000 |
commit | f652084a13da1765b04e52b92103a65fbf7636e9 (patch) | |
tree | 6f0002d2e1512736731e48cbaa93052abda8ce71 | |
parent | 568654cd247a5a5bc6c0e0136e385052da1a7d59 (diff) | |
download | chrome-ec-f652084a13da1765b04e52b92103a65fbf7636e9.tar.gz |
Revert "npcx: pwm: Use DCRn greater than CTRn to present its duty cycle is zero."
This reverts commit 3d27e8948e3cc1de0a4317deee69bcbd92159267.
Reason for revert: fan_is_stalled is broken.
Original change's description:
> npcx: pwm: Use DCRn greater than CTRn to present its duty cycle is zero.
>
> In npcx pwm driver, it turns off pwm module directly when its duty cycle
> is set to zero. But we saw pwm signal isn't turned off by the following
> sequence:
> 1. pwm_set_raw_duty(ch, 0);
> 2. pwm_enable(ch, 1);
>
> Please notice setting zero in DCRn doesn't mean duty cycle is zero.
> (NPCX duty cycle: ( (DCRn+1) / (CTRn+1) ) x 100). Hence in step 2, we
> can observe a very low duty cycle once the driver enables pwm module.
>
> According to figure. 24 in npcx5's datasheet, setting DCRn greater than
> CTRn means that the result of 16-bits comparator is always false. It
> equals the duty cycle is zero. This CL adopts this method to present it
> and removes the dependency between pwm_enable()/ pwm_get_enabled() and
> pwm_set_raw_duty()/pwm_get_duty().
>
> In order to make sure DCRn can be greater than CTRn, we also defined
> the PWN maximum duty cycle is (0xFFFF -1) since both DCR and CTR are
> 16-bits registers.
>
> BRANCH=none
> BUG=b:123552920
> TEST=No build errors for npcx5/7 series.
>
> Test pwm console command on npcx5/7 evbs by the following sequence.
> 1. pwm_set_raw_duty(ch, 0);
> 2. pwm_enable(ch, 1);
> And no symptoms are observed. PWM_CONFIG_ACTIVE_LOW flag is tested also
> and no symptom occurred.
>
> Test fan control by faninfo & fanset console commands. Connect Sunon
> 4-pins PWM fan and evb by following steps:
> 1. Connect PWM0 to PWM pin of fan.
> 2. Connect TA1_TACH1 and 3.3 PU on Tacho pin of fan.
> 3. Connect 5V and GND pins of fan to power supply.
> No symptoms are observed.
>
> Change-Id: I92517ff0bf3e027ae191be00112cd71ec4b55a2b
> Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
> Reviewed-on: https://chromium-review.googlesource.com/1475096
> Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
> (cherry picked from commit 93d7bcea8121869520b0d02bf94f95eb261bee05)
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1490675
> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
> Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Bug: b:123552920
Change-Id: Ie6e5c9328f133dd5138ee07c87751c37e9080d67
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1505015
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
-rw-r--r-- | chip/npcx/pwm.c | 24 | ||||
-rw-r--r-- | chip/npcx/pwm_chip.h | 3 | ||||
-rw-r--r-- | include/pwm.h | 6 |
3 files changed, 21 insertions, 12 deletions
diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c index 13af516bb9..b452b00beb 100644 --- a/chip/npcx/pwm.c +++ b/chip/npcx/pwm.c @@ -55,7 +55,7 @@ enum npcx_pwm_heartbeat_mode { * @param freq desired PWM frequency * @notes changed when initialization */ -static void pwm_set_freq(enum pwm_channel ch, uint32_t freq) +void pwm_set_freq(enum pwm_channel ch, uint32_t freq) { int mdl = pwm_channels[ch].channel; uint32_t clock; @@ -78,11 +78,8 @@ static void pwm_set_freq(enum pwm_channel ch, uint32_t freq) /* Calculate prescaler */ pre = DIV_ROUND_UP(clock, (0xffff * freq)); - /* - * Calculate maximum resolution for the given freq. and prescaler. And - * prevent it exceed the resolution of CTR/DCR registers. - */ - pwm_res[ch] = MIN((clock / pre) / freq, NPCX_PWM_MAX_RAW_DUTY); + /* Calculate maximum resolution for the given freq. and prescaler */ + pwm_res[ch] = (clock / pre) / freq; /* Set PWM prescaler. */ NPCX_PRSC(mdl) = pre - 1; @@ -99,6 +96,7 @@ static void pwm_set_freq(enum pwm_channel ch, uint32_t freq) * * @param ch operation channel * @param enabled enabled flag + * @return none */ void pwm_enable(enum pwm_channel ch, int enabled) { @@ -125,6 +123,7 @@ int pwm_get_enabled(enum pwm_channel ch) * * @param ch operation channel * @param percent duty cycle percent + * @return none */ void pwm_set_duty(enum pwm_channel ch, int percent) { @@ -137,6 +136,7 @@ void pwm_set_duty(enum pwm_channel ch, int percent) * * @param ch operation channel * @param duty cycle duty + * @return none */ void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty) { @@ -155,8 +155,10 @@ void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty) /* duty ranges from 0 - 0xffff, so scale down to 0 - pwm_res[ch] */ sd = DIV_ROUND_NEAREST(duty * pwm_res[ch], EC_PWM_MAX_DUTY); - /* Set the duty cycle. If it is zero, set DCR > CTR */ - NPCX_DCR(mdl) = sd ? sd : NPCX_PWM_MAX_RAW_DUTY + 1; + /* Set the duty cycle */ + NPCX_DCR(mdl) = (uint16_t)sd; + + pwm_enable(ch, !!duty); } /** @@ -182,7 +184,7 @@ uint16_t pwm_get_raw_duty(enum pwm_channel ch) int mdl = pwm_channels[ch].channel; /* Return duty */ - if (NPCX_DCR(mdl) > NPCX_CTR(mdl)) + if (!pwm_get_enabled(ch)) return 0; else /* @@ -197,6 +199,7 @@ uint16_t pwm_get_raw_duty(enum pwm_channel ch) * PWM configuration. * * @param ch operation channel + * @return none */ void pwm_config(enum pwm_channel ch) { @@ -230,6 +233,9 @@ void pwm_config(enum pwm_channel ch) /** * PWM initial. + * + * @param none + * @return none */ static void pwm_init(void) { diff --git a/chip/npcx/pwm_chip.h b/chip/npcx/pwm_chip.h index 3a658f5d62..c73855916f 100644 --- a/chip/npcx/pwm_chip.h +++ b/chip/npcx/pwm_chip.h @@ -21,7 +21,4 @@ struct pwm_t { extern const struct pwm_t pwm_channels[]; void pwm_config(enum pwm_channel ch); -/* Npcx PWM maximum duty cycle value */ -#define NPCX_PWM_MAX_RAW_DUTY (UINT16_MAX - 1) - #endif /* __CROS_EC_PWM_CHIP_H */ diff --git a/include/pwm.h b/include/pwm.h index 15413c537c..24b89332fc 100644 --- a/include/pwm.h +++ b/include/pwm.h @@ -20,6 +20,12 @@ void pwm_enable(enum pwm_channel ch, int enabled); int pwm_get_enabled(enum pwm_channel ch); /** + * Set PWM channel frequency (Hz). + * PWM will be disabled until the duty is set. + */ +void pwm_set_freq(enum pwm_channel ch, uint32_t freq); + +/** * Set PWM channel duty cycle (0-65535). */ void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty); |