kevin: Initial board commit

Initial EC board support for kevin, a npcx5m5g part with SPI host
interface.

BUG=chrome-os-partner:50819
BRANCH=None
TEST=`make BOARD=kevin`

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0d878edd7e8c7f59cfcb8e16637a5b589552eba9
Reviewed-on: https://chromium-review.googlesource.com/330856
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>

7 files changed, 785 insertions, 0 deletions

diff --git a/board/kevin/Makefile b/board/kevin/Makefile
new file mode 120000
index 0000000000..94aaae2c4d
--- /dev/null
+++ b/board/kevin/Makefile
@@ -0,0 +1 @@
+../../Makefile
\ No newline at end of file
diff --git a/board/kevin/board.c b/board/kevin/board.c
new file mode 100644
index 0000000000..0ff39634bc
--- /dev/null
+++ b/board/kevin/board.c
@@ -0,0 +1,134 @@
+/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "backlight.h"
+#include "button.h"
+#include "common.h"
+#include "driver/tcpm/fusb302.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "registers.h"
+#include "shi_chip.h"
+#include "switch.h"
+#include "timer.h"
+#include "thermal.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	/* Exchange status with TCPCs */
+	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
+}
+
+#include "gpio_list.h"
+
+/******************************************************************************/
+/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
+const struct adc_t adc_channels[] = {
+	[ADC_BOARD_ID] = {
+		"BOARD_ID", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PP900_AP] = {
+		"PP900_AP", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PP1200_LPDDR] = {
+		"PP1200_LPDDR", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PPVAR_CLOGIC] = {
+		"PPVAR_CLOGIC",
+		NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+	[ADC_PPVAR_LOGIC] = {
+		"PPVAR_LOGIC", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/******************************************************************************/
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_KBLIGHT] = { 2, 0, 10000 },
+	[PWM_CH_LED] =     { 3, PWM_CONFIG_DSLEEP_CLK, 100 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"tcpc0",   NPCX_I2C_PORT0_0, 1000, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
+	{"tcpc1",   NPCX_I2C_PORT0_1, 1000, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
+	{"sensors", NPCX_I2C_PORT1,   1000, GPIO_I2C1_SCL,  GPIO_I2C1_SDA},
+	{"charger", NPCX_I2C_PORT2,    400, GPIO_I2C2_SCL,  GPIO_I2C2_SDA},
+	{"battery", NPCX_I2C_PORT3,    400, GPIO_I2C3_SCL,  GPIO_I2C3_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/******************************************************************************/
+/* Wake-up pins for hibernate */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* Keyboard scan setting */
+struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 40,
+	.debounce_down_us = 6 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 1500,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = SECOND,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8  /* full set */
+	},
+};
+
+const struct button_config buttons[CONFIG_BUTTON_COUNT] = {
+	{"Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
+	 30 * MSEC, 0},
+	{"Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L,
+	 30 * MSEC, 0},
+};
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = {
+	{I2C_PORT_TCPC0, FUSB302_I2C_SLAVE_ADDR},
+	{I2C_PORT_TCPC1, FUSB302_I2C_SLAVE_ADDR},
+};
+
+void board_reset_pd_mcu(void)
+{
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_L))
+		status |= PD_STATUS_TCPC_ALERT_0;
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_L))
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int board_set_active_charge_port(int charge_port)
+{
+	/* TODO: Select proper charge port through BD99955 regs. */
+	ASSERT(charge_port != 1);
+	return EC_SUCCESS;
+}
+
+void board_set_charge_limit(int charge_ma)
+{
+	/* TODO: Add support for BD99955 charger. */
+}
diff --git a/board/kevin/board.h b/board/kevin/board.h
new file mode 100644
index 0000000000..9382221f9a
--- /dev/null
+++ b/board/kevin/board.h
@@ -0,0 +1,115 @@
+/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Configuration for Nuvoton M4 EB */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Optional modules */
+#define CONFIG_ADC
+#define CONFIG_PWM
+#define CONFIG_HOSTCMD_SPS /* Used in ARM-based platform for host interface */
+
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
+
+/* Optional features */
+#define CONFIG_BUTTON_COUNT        2
+#define CONFIG_FLASH_SIZE          0x00080000 /* 512KB spi flash */
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard */
+#define CONFIG_POWER_BUTTON
+#define CONFIG_PWM_KBLIGHT
+/* TODO: Verify W25Q40 protect regs are compatible with W25X40 */
+#define CONFIG_SPI_FLASH_W25X40
+#define CONFIG_VBOOT_HASH
+
+/* USB PD config */
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_CUSTOM_VDM
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_LOG_SIZE 512
+#define CONFIG_USB_PD_PORT_COUNT 2
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define CONFIG_USB_PD_TCPM_VBUS
+/* TODO: Enable TRY_SRC */
+#undef CONFIG_USB_PD_TRY_SRC
+
+#define CONFIG_BATTERY_SMART
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L
+
+/* TODO: Allow higher voltage charging */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW       15000
+#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_VOLTAGE_MV     5000
+
+/* TODO: determine the following board specific type-C power constants */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+
+/* start as a sink in case we have no other power supply/battery */
+#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
+
+/* Optional features for test commands */
+#define CONFIG_CMD_TASKREADY
+#define CONFIG_CMD_STACKOVERFLOW
+#define CONFIG_CMD_JUMPTAGS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI_FLASH
+#define CONFIG_CMD_SCRATCHPAD
+
+#define CONFIG_UART_HOST                0
+
+/* Optional feature - used by nuvoton */
+#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_TACH_SEL2       0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */
+
+/* Optional for testing */
+#undef  CONFIG_PECI
+#undef  CONFIG_PSTORE
+#undef  CONFIG_LOW_POWER_IDLE           /* Deep Sleep Support */
+
+#define I2C_PORT_TCPC0    NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1    NPCX_I2C_PORT0_1
+#define I2C_PORT_CHARGER  NPCX_I2C_PORT2
+#define I2C_PORT_BATTERY  NPCX_I2C_PORT3
+
+#ifndef __ASSEMBLER__
+
+enum adc_channel {
+	/* No VBUS ADC channel on kevin */
+	ADC_VBUS = -1,
+	/* Real ADC channels begin here */
+	ADC_BOARD_ID = 0,
+	ADC_PP900_AP,
+	ADC_PP1200_LPDDR,
+	ADC_PPVAR_CLOGIC,
+	ADC_PPVAR_LOGIC,
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+	PWM_CH_LED,
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+void board_reset_pd_mcu(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kevin/build.mk b/board/kevin/build.mk
new file mode 100644
index 0000000000..34d772b275
--- /dev/null
+++ b/board/kevin/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+# the IC is Nuvoton M-Series EC (npcx5m5g, npcx5m6g)
+CHIP:=npcx
+CHIP_VARIANT:=npcx5m5g
+
+board-y=board.o
+board-y+=usb_pd_policy.o
diff --git a/board/kevin/ec.tasklist b/board/kevin/ec.tasklist
new file mode 100644
index 0000000000..7f4b6feb66
--- /dev/null
+++ b/board/kevin/ec.tasklist
@@ -0,0 +1,27 @@
+/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' is the name of the task
+ * 'r' is the main routine of the task
+ * 'd' is an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
+
diff --git a/board/kevin/gpio.inc b/board/kevin/gpio.inc
new file mode 100644
index 0000000000..5b5d4f66c4
--- /dev/null
+++ b/board/kevin/gpio.inc
@@ -0,0 +1,144 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+
+GPIO_INT(WP_L,             PIN(9, 3), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(SHI_CS_L,         PIN(5, 3), GPIO_INT_FALLING, shi_cs_event)
+GPIO_INT(USB_C0_PD_INT_L,  PIN(6, 0), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(USB_C1_PD_INT_L,  PIN(6, 2), GPIO_INT_FALLING | GPIO_PULL_UP,
+         tcpc_alert_event)
+GPIO_INT(VOLUME_UP_L,      PIN(8, 2), GPIO_INT_BOTH | GPIO_INPUT | GPIO_PULL_UP,
+         button_interrupt)
+GPIO_INT(VOLUME_DOWN_L,    PIN(8, 3), GPIO_INT_BOTH | GPIO_INPUT | GPIO_PULL_UP,
+         button_interrupt)
+GPIO_INT(POWER_BUTTON_L,   PIN(0, 4), GPIO_INT_BOTH | GPIO_INPUT,
+         power_button_interrupt)
+GPIO_INT(LID_OPEN,         PIN(9, 7), GPIO_INT_BOTH | GPIO_INPUT | GPIO_SEL_1P8V,
+         lid_interrupt)
+
+/* TODO: Add power sequencing interrupt pins */
+
+/* VR EN */
+GPIO(AP_CORE_EN,           PIN(7, 2), GPIO_OUT_LOW)
+GPIO(LPDDR_PWR_EN,         PIN(8, 6), GPIO_OUT_LOW)
+GPIO(PPVAR_CLOGIC_EN,      PIN(C, 5), GPIO_OUT_LOW)
+GPIO(PPVAR_LOGIC_EN,       PIN(8, 5), GPIO_OUT_LOW)
+
+GPIO(PP900_AP_EN,          PIN(B, 7), GPIO_OUT_LOW)
+GPIO(PP900_DDRPLL_EN,      PIN(C, 0), GPIO_OUT_LOW)
+GPIO(PP900_PLL_EN,         PIN(C, 1), GPIO_OUT_LOW)
+GPIO(PP900_PMU_EN,         PIN(C, 2), GPIO_OUT_LOW)
+GPIO(PP900_USB_EN,         PIN(A, 5), GPIO_OUT_LOW)
+GPIO(PP900_PCIE_EN,        PIN(0, 0), GPIO_OUT_LOW)
+
+GPIO(PP1200_HSIC_EN,       PIN(8, 1), GPIO_OUT_LOW)
+
+GPIO(PP1800_SENSOR_EN_L,   PIN(A, 7), GPIO_OUT_HIGH)
+GPIO(PP1800_AUDIO_EN_L,    PIN(A, 6), GPIO_OUT_HIGH)
+GPIO(PP1800_LID_EN_L,      PIN(B, 0), GPIO_OUT_HIGH)
+GPIO(PP1800_PMU_EN_L,      PIN(5, 1), GPIO_OUT_HIGH)
+GPIO(PP1800_AP_AVDD_EN_L,  PIN(5, 2), GPIO_OUT_HIGH)
+GPIO(PP1800_USB_EN_L,      PIN(C, 3), GPIO_OUT_HIGH)
+GPIO(PP1800_S0_EN_L,       PIN(5, 0), GPIO_OUT_HIGH)
+GPIO(PP1800_SIXAXIS_EN_L,  PIN(5, 6), GPIO_OUT_HIGH)
+
+GPIO(PP3300_TRACKPAD_EN_L, PIN(3, 2), GPIO_OUT_HIGH)
+GPIO(PP3300_USB_EN_L,      PIN(3, 7), GPIO_OUT_HIGH)
+
+GPIO(PP5000_EN,            PIN(C, 6), GPIO_OUT_LOW)
+
+GPIO(PP5000_PG,            PIN(7, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(TPS65261_PG,          PIN(7, 5), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(AP_EC_S3_S0_L,        PIN(5, 4), GPIO_INPUT)
+GPIO(AP_CORE_PG,           PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C0_SCL0,            PIN(B, 5), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C0_SDA0,            PIN(B, 4), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C0_SCL1,            PIN(B, 3), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C0_SDA1,            PIN(B, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C1_SCL,             PIN(9, 0), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C1_SDA,             PIN(8, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V)
+GPIO(I2C2_SCL,             PIN(9, 2), GPIO_ODR_HIGH)
+GPIO(I2C2_SDA,             PIN(9, 1), GPIO_ODR_HIGH)
+GPIO(I2C3_SCL,             PIN(D, 1), GPIO_ODR_HIGH)
+GPIO(I2C3_SDA,             PIN(D, 0), GPIO_ODR_HIGH)
+
+/* TODO - configure 32KCLKIN for alternate mode */
+GPIO(CLK_32K_IN,           PIN(E, 7), GPIO_INPUT)
+
+/* TODO - check if internal PU is needed */
+GPIO(LID_ACCEL_INT_L,      PIN(C, 7), GPIO_INPUT | GPIO_PULL_UP)
+
+
+GPIO(C0_VOUT_EN_L,         PIN(D, 3), GPIO_OUT_HIGH)
+GPIO(C1_VOUT_EN_L,         PIN(D, 2), GPIO_OUT_HIGH)
+
+GPIO(ENTERING_RW,          PIN(7, 6), GPIO_OUT_LOW)
+GPIO(SYS_RST,              PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EC_INT_L,             PIN(5, 7), GPIO_OUT_HIGH)
+GPIO(EC_BOARD_ID_EN_L,     PIN(3, 5), GPIO_OUT_HIGH)
+
+/* NC */
+GPIO(STRAP_ENG_L,          PIN(B, 6), GPIO_OUT_LOW)
+GPIO(USB_DP_HPD,           PIN(6, 6), GPIO_OUT_LOW)
+GPIO(CHARGER_RESET_L,      PIN(0, 1), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(CR50_RESET_L,         PIN(0, 2), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(CHARGER_INT_L,        PIN(3, 3), GPIO_INPUT)
+GPIO(EC_BATT_PRES_L,       PIN(3, 4), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(LID_360_L,            PIN(3, 6), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(BASE_SIXAXIS_INT_L,   PIN(4, 0), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(CCD_MODE,             PIN(6, 3), GPIO_INPUT)
+GPIO(USB_A_EN,             PIN(7, 0), GPIO_OUT_LOW)
+GPIO(WARM_RESET_REQ,       PIN(7, 3), GPIO_INPUT)
+GPIO(AP_OVERTEMP,          PIN(7, 4), GPIO_INPUT)
+GPIO(USB_A_CHARGE_EN,      PIN(8, 4), GPIO_INPUT)
+GPIO(SPI_SENSOR_CS_L,      PIN(9, 4), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+
+
+GPIO(USB_C0_DISCHARGE,     PIN(0, 3), GPIO_OUT_LOW)
+GPIO(USB_C1_DISCHARGE,     PIN(B, 1), GPIO_OUT_LOW)
+/* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
+ALTERNATE(PIN_MASK(A, 0x0A), 1,  MODULE_SPI,           0)
+/* SPIP_MISO GPIO95 */
+ALTERNATE(PIN_MASK(9, 0x20), 1,  MODULE_SPI,           0)
+/* I2C0SDA1/I2C0SCL1 GPIOB2/B3 */
+ALTERNATE(PIN_MASK(B, 0x0C), 1,  MODULE_I2C,           0)
+/* I2C0SDA0/I2C0SCL0 GPIOB4/B5 */
+ALTERNATE(PIN_MASK(B, 0x30), 1,  MODULE_I2C,           0)
+/* I2C1SDA GPIO87 */
+ALTERNATE(PIN_MASK(8, 0x80), 1,  MODULE_I2C,           0)
+/* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */
+ALTERNATE(PIN_MASK(9, 0x07), 1,  MODULE_I2C,           0)
+/* I2C3SDA/I2C3SCL GPIOD0/D1    */
+ALTERNATE(PIN_MASK(D, 0x03), 1,  MODULE_I2C,           0)
+/* PWM2 / BLPWM */
+ALTERNATE(PIN_MASK(C, 0x10), 1,  MODULE_PWM,           0)
+/* PWM3 / CHGLED */
+ALTERNATE(PIN_MASK(8, 0x01), 1,  MODULE_PWM,           0)
+/* CR_SIN/SOUT GPIO64/65 */
+ALTERNATE(PIN_MASK(6, 0x30), 1,  MODULE_UART,          0)
+/* ADC0-4 */
+ALTERNATE(PIN_MASK(4, 0x3e), 1,  MODULE_ADC,           0)
+
+/* Keyboard Columns */
+ALTERNATE(PIN_MASK(0, 0xE0), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(1, 0xFF), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(2, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
+
+/* Keyboard Rows */
+ALTERNATE(PIN_MASK(2, 0xFC), 0,  MODULE_KEYBOARD_SCAN, 0)
+ALTERNATE(PIN_MASK(3, 0x03), 0,  MODULE_KEYBOARD_SCAN, 0)
diff --git a/board/kevin/usb_pd_policy.c b/board/kevin/usb_pd_policy.c
new file mode 100644
index 0000000000..48a6cf6064
--- /dev/null
+++ b/board/kevin/usb_pd_policy.c
@@ -0,0 +1,350 @@
+/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "charge_manager.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
+			 PDO_FIXED_COMM_CAP)
+
+/* TODO: fill in correct source and sink capabilities */
+const uint32_t pd_src_pdo[] = {
+		PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+		PDO_BATT(4750, 21000, 15000),
+		PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+int pd_is_valid_input_voltage(int mv)
+{
+	return 1;
+}
+
+void pd_transition_voltage(int idx)
+{
+	/* No-operation: we are always 5V */
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Disable charging */
+	/* TODO: Add support for BD99955 */
+
+	/* Provide VBUS */
+	gpio_set_level(port ? GPIO_C1_VOUT_EN_L :
+			      GPIO_C0_VOUT_EN_L, 1);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	gpio_set_level(port ? GPIO_C1_VOUT_EN_L :
+			      GPIO_C0_VOUT_EN_L, 0);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+void pd_set_input_current_limit(int port, uint32_t max_ma,
+				uint32_t supply_voltage)
+{
+#ifdef CONFIG_CHARGE_MANAGER
+	struct charge_port_info charge;
+
+	charge.current = max_ma;
+	charge.voltage = supply_voltage;
+	charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge);
+#endif
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+void typec_set_input_current_limit(int port, uint32_t max_ma,
+				   uint32_t supply_voltage)
+{
+#ifdef CONFIG_CHARGE_MANAGER
+	struct charge_port_info charge;
+
+	charge.current = max_ma;
+	charge.voltage = supply_voltage;
+	charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge);
+#endif
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
+int pd_check_power_swap(int port)
+{
+	/*
+	 * Allow power swap as long as we are acting as a dual role device,
+	 * otherwise assume our role is fixed (not in S0 or console command
+	 * to fix our role).
+	 */
+	return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0;
+}
+
+int pd_check_data_swap(int port, int data_role)
+{
+	/* Allow data swap if we are a UFP, otherwise don't allow */
+	return (data_role == PD_ROLE_UFP) ? 1 : 0;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* TODO: Make sure we can source 5V in G3 */
+	return 1;
+}
+
+void pd_execute_data_swap(int port, int data_role)
+{
+	/* Do nothing */
+}
+
+void pd_check_pr_role(int port, int pr_role, int flags)
+{
+	/*
+	 * If partner is dual-role power and dualrole toggling is on, consider
+	 * if a power swap is necessary.
+	 */
+	if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
+	    pd_get_dual_role() == PD_DRP_TOGGLE_ON) {
+		/*
+		 * If we are a sink and partner is not externally powered, then
+		 * swap to become a source. If we are source and partner is
+		 * externally powered, swap to become a sink.
+		 */
+		int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER;
+
+		if ((!partner_extpower && pr_role == PD_ROLE_SINK) ||
+		     (partner_extpower && pr_role == PD_ROLE_SOURCE))
+			pd_request_power_swap(port);
+	}
+}
+
+void pd_check_dr_role(int port, int dr_role, int flags)
+{
+	/* If UFP, try to switch to DFP */
+	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
+		pd_request_data_swap(port);
+}
+/* ----------------- Vendor Defined Messages ------------------ */
+const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+
+int pd_custom_vdm(int port, int cnt, uint32_t *payload,
+		  uint32_t **rpayload)
+{
+	int cmd = PD_VDO_CMD(payload[0]);
+	uint16_t dev_id = 0;
+	int is_rw;
+
+	/* make sure we have some payload */
+	if (cnt == 0)
+		return 0;
+
+	switch (cmd) {
+	case VDO_CMD_VERSION:
+		/* guarantee last byte of payload is null character */
+		*(payload + cnt - 1) = 0;
+		CPRINTF("version: %s\n", (char *)(payload+1));
+		break;
+	case VDO_CMD_READ_INFO:
+	case VDO_CMD_SEND_INFO:
+		/* copy hash */
+		if (cnt == 7) {
+			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
+			is_rw = VDO_INFO_IS_RW(payload[6]);
+
+			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
+				HW_DEV_ID_MAJ(dev_id),
+				HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]),
+				is_rw);
+		} else if (cnt == 6) {
+			/* really old devices don't have last byte */
+			pd_dev_store_rw_hash(port, dev_id, payload + 1,
+					     SYSTEM_IMAGE_UNKNOWN);
+		}
+		break;
+	case VDO_CMD_CURRENT:
+		CPRINTF("Current: %dmA\n", payload[1]);
+		break;
+	case VDO_CMD_FLIP:
+		/* usb_mux_flip(port); */
+		break;
+#ifdef CONFIG_USB_PD_LOGGING
+	case VDO_CMD_GET_LOG:
+		pd_log_recv_vdm(port, cnt, payload);
+		break;
+#endif /* CONFIG_USB_PD_LOGGING */
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+static int dp_flags[CONFIG_USB_PD_PORT_COUNT];
+/* DP Status VDM as returned by UFP */
+static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT];
+
+static void svdm_safe_dp_mode(int port)
+{
+	/* make DP interface safe until configure */
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	/* usb_mux_set(port, TYPEC_MUX_NONE,
+		    USB_SWITCH_CONNECT, pd_get_polarity(port)); */
+}
+
+static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		svdm_safe_dp_mode(port);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int svdm_dp_status(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_STATUS | VDO_OPOS(opos));
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
+				   0, /* power low? ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)));
+	return 2;
+};
+
+static int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+	/* int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); */
+	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
+
+	if (!pin_mode)
+		return 0;
+
+	/* usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP,
+		    USB_SWITCH_CONNECT, pd_get_polarity(port)); */
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
+				1,             /* DPv1.3 signaling */
+				2);            /* UFP connected */
+	return 2;
+};
+
+static void svdm_dp_post_config(int port)
+{
+	/* TODO: Figure out HPD */
+}
+
+static int svdm_dp_attention(int port, uint32_t *payload)
+{
+	/* TODO: Figure out HPD */
+	return 1;
+}
+
+static void svdm_exit_dp_mode(int port)
+{
+	/* TODO: Figure out HPD */
+}
+
+static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
+{
+	/* Always enter GFU mode */
+	return 0;
+}
+
+static void svdm_exit_gfu_mode(int port)
+{
+}
+
+static int svdm_gfu_status(int port, uint32_t *payload)
+{
+	/*
+	 * This is called after enter mode is successful, send unstructured
+	 * VDM to read info.
+	 */
+	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
+	return 0;
+}
+
+static int svdm_gfu_config(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+static int svdm_gfu_attention(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+const struct svdm_amode_fx supported_modes[] = {
+	{
+		.svid = USB_SID_DISPLAYPORT,
+		.enter = &svdm_enter_dp_mode,
+		.status = &svdm_dp_status,
+		.config = &svdm_dp_config,
+		.post_config = &svdm_dp_post_config,
+		.attention = &svdm_dp_attention,
+		.exit = &svdm_exit_dp_mode,
+	},
+	{
+		.svid = USB_VID_GOOGLE,
+		.enter = &svdm_enter_gfu_mode,
+		.status = &svdm_gfu_status,
+		.config = &svdm_gfu_config,
+		.attention = &svdm_gfu_attention,
+		.exit = &svdm_exit_gfu_mode,
+	}
+};
+const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
+