diff options
| author | Philip Chen <philipchen@google.com> | 2018-01-13 22:47:22 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-01-23 20:18:28 -0800 |
| commit | 163ba57cc2507774655d3194aaf4b83fa970202a (patch) | |
| tree | 60d07e33eff181be6cf88424457037931f6c50c5 | |
| parent | 451fba34b88b45aaac77186d98c5a6481154837a (diff) | |
| download | chrome-ec-163ba57cc2507774655d3194aaf4b83fa970202a.tar.gz | |
scarlet: Assert SYS_RST_L in S5
To support CR50 deep sleep mode:
In up-sequence, SYS_RST_L needs to remain asserted on the transition
to S5 and then deasserted on the transition to S0;
In down-sequence, SYS_RST_L needs to be asserted on the transition to S5.
This only affects Scarlet.
BUG=b:35647982
BRANCH=none
TEST=minitor SYS_RST_L pin to confirm it is toggled right
Change-Id: Ic73d39c531f9d28b2087a23d58613e98ec80dbd2
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/866115
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/scarlet/gpio.inc | 2 | ||||
| -rw-r--r-- | power/rk3399.c | 12 |
2 files changed, 12 insertions, 2 deletions
diff --git a/board/scarlet/gpio.inc b/board/scarlet/gpio.inc index 58c71bf4e0..8e382b774e 100644 --- a/board/scarlet/gpio.inc +++ b/board/scarlet/gpio.inc @@ -82,7 +82,7 @@ GPIO(BATT_ID, PIN(C, 2), GPIO_INPUT | GPIO_PULL_UP) /* Other output pins */ GPIO(ENTERING_RW, PIN(C, 6), GPIO_ODR_HIGH) -GPIO(SYS_RST_L, PIN(C, 8), GPIO_ODR_HIGH) +GPIO(SYS_RST_L, PIN(C, 8), GPIO_ODR_LOW) GPIO(EC_INT_L, PIN(E, 3), GPIO_ODR_HIGH) GPIO(EC_BOARD_ID_EN_L, PIN(F, 1), GPIO_ODR_HIGH) GPIO(USB_C0_DISCHARGE, PIN(A, 11), GPIO_OUT_LOW) diff --git a/power/rk3399.c b/power/rk3399.c index b264816f72..fb7a437ef1 100644 --- a/power/rk3399.c +++ b/power/rk3399.c @@ -54,6 +54,8 @@ #define S3_USB_WAKE /* This board has non-INT power signal pins */ #define POWER_SIGNAL_POLLING + /* This board supports CR50 deep sleep mode */ + #define CR50_DEEP_SLEEP /* * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the * signal every 5ms, up to 200 times (~ 1 second timeout). @@ -94,7 +96,6 @@ BUILD_ASSERT(GPIO_COUNT < 256); static const struct power_seq_op s5s3_power_seq[] = { { GPIO_PP900_S0_EN, 1, 2 }, { GPIO_PP900_S3_EN, 1, 2 }, - { GPIO_SYS_RST_L, 0, 0 }, { GPIO_PP3300_S3_EN, 1, 2 }, { GPIO_PP1800_S3_EN, 1, 2 }, { GPIO_PP1250_S3_EN, 1, 2 }, @@ -175,6 +176,7 @@ static const struct power_seq_op s0s3_usb_wake_power_seq[] = { /* The power sequence for POWER_S3S5 */ #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2 static const struct power_seq_op s3s5_power_seq[] = { + { GPIO_SYS_RST_L, 0, 0 }, { GPIO_PP1250_S3_EN, 0, 2 }, { GPIO_PP1800_S3_EN, 0, 2 }, { GPIO_PP3300_S3_EN, 0, 2 }, @@ -312,7 +314,9 @@ static int power_seq_run(const struct power_seq_op *power_seq_ops, int op_count) enum power_state power_handle_state(enum power_state state) { +#ifndef CR50_DEEP_SLEEP static int sys_reset_asserted; +#endif #ifdef S3_USB_WAKE static int usb_wake_enabled; #endif @@ -392,11 +396,13 @@ enum power_state power_handle_state(enum power_state state) case POWER_S5S3: power_seq_run(s5s3_power_seq, ARRAY_SIZE(s5s3_power_seq)); +#ifndef CR50_DEEP_SLEEP /* * Assert SYS_RST now, to be released in S3S0, to avoid * resetting the TPM soon after power-on. */ sys_reset_asserted = 1; +#endif if (power_wait_signals(IN_PGOOD_S3)) { chipset_force_shutdown(); @@ -419,13 +425,17 @@ enum power_state power_handle_state(enum power_state state) #endif power_seq_run(s3s0_power_seq, ARRAY_SIZE(s3s0_power_seq)); +#ifndef CR50_DEEP_SLEEP /* Release SYS_RST if we came from S5 */ if (sys_reset_asserted) { +#endif msleep(10); gpio_set_level(GPIO_SYS_RST_L, 1); +#ifndef CR50_DEEP_SLEEP sys_reset_asserted = 0; } +#endif #ifdef POWER_SIGNAL_POLLING /* |