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| author | Peter Marheine <pmarheine@chromium.org> | 2022-06-02 11:34:57 +1000 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-03 00:12:45 +0000 |
| commit | bcfa74e7197e543329e2d38e5b8c1daa602458e8 (patch) | |
| tree | 543ab0bcf0737c90dc9861dc78c0856759f4e091 | |
| parent | 4407d633fba8728f670b7b96b917d25a45bebbe5 (diff) | |
| download | chrome-ec-bcfa74e7197e543329e2d38e5b8c1daa602458e8.tar.gz | |
Replace power_get_state calls with chipset_in_state
The `power_get_state` function does not exist when using the Zephyr native
power sequencing subsystem. Use the chipset_in_state family of functions
instead, because those are available in either configuration.
For PD power state change, this means S4 cannot be returned because
chipset_in_state doesn't currently provide an option for S4 specifically.
BUG=b:233681784
TEST=make buildall; zmake testall
BRANCH=none
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I14af373ec4473b0c19bf46ebae0c503e5139e114
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3685929
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Jameson Thies <jthies@google.com>
Tested-by: Jameson Thies <jthies@google.com>
| -rw-r--r-- | common/usbc/usb_pd_dpm.c | 42 | ||||
| -rw-r--r-- | driver/temp_sensor/amd_r19me4070.c | 2 |
2 files changed, 13 insertions, 31 deletions
diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c index 734fe53926..745454b647 100644 --- a/common/usbc/usb_pd_dpm.c +++ b/common/usbc/usb_pd_dpm.c @@ -888,41 +888,23 @@ static uint8_t get_status_power_state_change(void) enum pd_sdb_power_state ret = PD_SDB_POWER_STATE_NOT_SUPPORTED; #ifdef HAS_TASK_CHIPSET - switch (power_get_state()) { - case POWER_G3: - case POWER_S5G3: + if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_HARD_OFF)) { ret = PD_SDB_POWER_STATE_G3; - break; - case POWER_S5: - case POWER_G3S5: - case POWER_S3S5: - case POWER_S4S5: + } else if (chipset_in_or_transitioning_to_state( + CHIPSET_STATE_SOFT_OFF)) { + /* + * SOFT_OFF includes S4; chipset_state API doesn't support S4 + * specifically, so fold S4 to S5 + */ ret = PD_SDB_POWER_STATE_S5; - break; - case POWER_S4: - case POWER_S3S4: - case POWER_S5S4: - ret = PD_SDB_POWER_STATE_S4; - break; - case POWER_S3: - case POWER_S5S3: - case POWER_S0S3: - case POWER_S4S3: + } else if (chipset_in_or_transitioning_to_state( + CHIPSET_STATE_SUSPEND)) { ret = PD_SDB_POWER_STATE_S3; - break; - case POWER_S0: - case POWER_S3S0: -#ifdef CONFIG_POWER_S0IX - case POWER_S0ixS0: -#endif /* CONFIG_POWER_S0IX */ + } else if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)) { ret = PD_SDB_POWER_STATE_S0; - break; -#ifdef CONFIG_POWER_S0IX - case POWER_S0ix: - case POWER_S0S0ix: + } else if (chipset_in_or_transitioning_to_state( + CHIPSET_STATE_STANDBY)) { ret = PD_SDB_POWER_STATE_MODERN_STANDBY; - break; -#endif /* CONFIG_POWER_S0IX */ } #endif /* HAS_TASK_CHIPSET */ diff --git a/driver/temp_sensor/amd_r19me4070.c b/driver/temp_sensor/amd_r19me4070.c index b331a1a3eb..b5f4e66d38 100644 --- a/driver/temp_sensor/amd_r19me4070.c +++ b/driver/temp_sensor/amd_r19me4070.c @@ -53,7 +53,7 @@ int get_temp_R19ME4070(int idx, int *temp_ptr) * We shouldn't read the GPU temperature when the state * is not in S0, because GPU is enabled in S0. */ - if ((power_get_state()) != POWER_S0) { + if (!chipset_in_state(CHIPSET_STATE_ON)) { *temp_ptr = C_TO_K(0); return EC_ERROR_BUSY; } |