diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2021-06-22 21:24:06 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-09-13 17:33:59 +0000 |
| commit | 193b7fcffe40413fd70e222ee52106baf0d844aa (patch) | |
| tree | 8d913e9e9727a4f068c9d016fc532230f344a07b | |
| parent | 5cc260eb5247184fb3df539a68ef7929407f1938 (diff) | |
| download | chrome-ec-193b7fcffe40413fd70e222ee52106baf0d844aa.tar.gz | |
chgstv2: Unify power-on and shutdown battery thresholds
Currently, power-on battery SoC and shutdown battery SoC are
independently configured by each board. This patch will unify the
setting as follows:
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%)
CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2 (shutdown if soc <= 2%)
BATTERY_LEVEL_SHUTDOWN = 3 (shutdown if soc < 3%)
CONFIG_BATTERY_EXPORT_DISPLAY_SOC = Y (removed)
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC = 1
This allows us to show the low battery alert whenever we can because
EC doesn't inhibit power-on even if it knows the host would
immediately shut down.
With CONFIG_BATTERY_EXPORT_DISPLAY_SOC, boards will start using the
CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2% as the low battery
threshold (and the SoC will be agreed between the EC and Powerd).
Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 1 will keep the
same threshold. This is for avoiding degrading the UX by increasing
the power-on threshold (even though a question that 1% may not be
enough for soft sync to finish consistently remains to be answered).
Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON > 2 will have a
lower threshold but we think 2% is enough to finish the software sync.
A lower threshold also improves the UX by showing the low battery
alert in the situation where otherwise the system would leave the user
uninformed by not responding to a power button press.
BUG=b:191837893
BRANCH=None
TEST=buildall
Change-Id: If6ff733bc181f929561a3fffb8a84e760668ce37
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981468
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3872712
29 files changed, 2930 insertions, 66 deletions
diff --git a/baseboard/asurada/baseboard.h b/baseboard/asurada/baseboard.h new file mode 100644 index 0000000000..97576a32ef --- /dev/null +++ b/baseboard/asurada/baseboard.h @@ -0,0 +1,196 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Asurada board configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +/* IT81202-bx config */ +/* + * NOTE: we need to make correct VCC voltage selection here if EC's VCC isn't + * connect to 1.8v on other versions. + */ +#define CONFIG_IT83XX_VCC_1P8V + +/* + * On power-on, H1 releases the EC from reset but then quickly asserts and + * releases the reset a second time. This means the EC sees 2 resets: + * (1) power-on reset, (2) reset-pin reset. This config will + * allow the second reset to be treated as a power-on. + */ +#define CONFIG_BOARD_RESET_AFTER_POWER_ON +#define CONFIG_BOARD_VERSION_CUSTOM +#define CONFIG_CHIPSET_MT8192 +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC +#define CONFIG_POWER_SLEEP_FAILURE_DETECTION +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE + +/* Chipset */ +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_CMD_POWERINDEBUG +#define CONFIG_HOST_COMMAND_STATUS +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_LOW_POWER_S0 +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_COMMON +#define CONFIG_PWM +#define CONFIG_VBOOT_HASH +#define CONFIG_VOLUME_BUTTONS +#define CONFIG_WP_ACTIVE_HIGH + +/* Battery */ +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_BATTERY_SMART + +/* BC12 */ +#define CONFIG_BC12_DETECT_MT6360 +#define CONFIG_BC12_DETECT_PI3USB9201 +#undef CONFIG_BC12_SINGLE_DRIVER +#define CONFIG_USB_CHARGER + +/* Charger */ +#define ADC_AMON_BMON ADC_CHARGER_AMON_R /* ADC name remap */ +#define ADC_PSYS ADC_CHARGER_PMON /* ADC name remap */ +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER +#define CONFIG_CHARGE_RAMP_HW +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_ISL9238C +#define CONFIG_CHARGER_MAINTAIN_VBAT +#define CONFIG_CHARGER_OTG +#define CONFIG_CHARGER_PSYS +#define CONFIG_CHARGER_PSYS_READ +#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */ +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */ +#define CONFIG_CMD_CHARGER_ADC_AMON_BMON + +/* Keyboard */ +#define CONFIG_CMD_KEYBOARD +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PROTOCOL_MKBP +#define CONFIG_MKBP_USE_GPIO + +/* I2C */ +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER +#define CONFIG_I2C_PASSTHRU_RESTRICTED +#define CONFIG_I2C_VIRTUAL_BATTERY +#define I2C_PORT_CHARGER IT83XX_I2C_CH_A +#define I2C_PORT_BATTERY IT83XX_I2C_CH_A +#define I2C_PORT_ACCEL IT83XX_I2C_CH_B +#define I2C_PORT_PPC0 IT83XX_I2C_CH_C +#define I2C_PORT_PPC1 IT83XX_I2C_CH_E +#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C +#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define CONFIG_SMBUS_PEC + +/* LED */ +#define CONFIG_LED_COMMON + +/* PD / USB-C / PPC */ +#define CONFIG_CMD_PPC_DUMP +#define CONFIG_HOSTCMD_PD_CONTROL +#define CONFIG_IT83XX_TUNE_CC_PHY +#define CONFIG_USB_MUX_VIRTUAL +#define CONFIG_USBC_PPC +#define CONFIG_USBC_PPC_DEDICATED_INT +#define CONFIG_USBC_PPC_POLARITY +#define CONFIG_USBC_PPC_SYV682C +#define CONFIG_USBC_PPC_VCONN +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP +#define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_MUX_IT5205 /* C0 */ +#define CONFIG_USB_MUX_PS8743 /* C1 */ +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_DECODE_SOP +#define CONFIG_USB_PD_DISCHARGE +#define CONFIG_USB_PD_DISCHARGE_PPC +#define CONFIG_USB_PD_DP_HPD_GPIO +#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_FRS_PPC +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_REV30 +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TCPMV2 +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_PD_VBUS_DETECT_PPC +#define CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT +#define CONFIG_USB_PID 0x5053 +#define CONFIG_USB_POWER_DELIVERY + +/* USB-A */ +#define CONFIG_USB_PORT_POWER_DUMB +#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK +#define USB_PORT_COUNT USBA_PORT_COUNT + +/* UART */ +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 4096 + +/* Sensor */ +#ifdef HAS_TASK_MOTIONSENSE +#define CONFIG_CMD_ACCEL_INFO +#define CONFIG_CMD_ACCELS + +#define CONFIG_ACCEL_FIFO +#define CONFIG_ACCEL_FIFO_SIZE 256 +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) +#define CONFIG_ACCEL_INTERRUPTS +#endif + +/* SPI / Host Command */ +#define CONFIG_SPI + +/* MKBP */ +#define CONFIG_MKBP_EVENT + +#define CONFIG_KEYBOARD_PROTOCOL_MKBP +#define CONFIG_MKBP_USE_GPIO + +/* Voltage regulator control */ +#define CONFIG_HOSTCMD_REGULATOR + +/* Define the host events which are allowed to wakeup AP in S3. */ +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* And the MKBP events */ +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ + BIT(EC_MKBP_EVENT_HOST_EVENT)) + +#include "baseboard_common.h" + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" +#include "power/mt8192.h" + +void board_reset_pd_mcu(void); +enum board_sub_board board_get_sub_board(void); +void usb_a0_interrupt(enum gpio_signal signal); + +#endif /* !__ASSEMBLER__ */ +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h new file mode 100644 index 0000000000..547349469d --- /dev/null +++ b/baseboard/brya/baseboard.h @@ -0,0 +1,239 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Brya baseboard configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +/* + * By default, enable all console messages excepted HC + */ +#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) + +/* NPCX9 config */ +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +/* + * This defines which pads (GPIO10/11 or GPIO64/65) are connected to + * the "UART1" (NPCX_UART_PORT0) controller when used for + * CONSOLE_UART. + */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ + +/* EC Defines */ +#define CONFIG_LTO +#define CONFIG_CBI_EEPROM +#define CONFIG_BOARD_VERSION_CBI +#define CONFIG_CRC8 +#define CONFIG_FPU + +/* Verified boot configs */ +#define CONFIG_VBOOT_EFS2 +#define CONFIG_VBOOT_HASH +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 + +#define CONFIG_HIBERNATE_PSL + +/* Work around double CR50 reset by waiting in initial power on. */ +#define CONFIG_BOARD_RESET_AFTER_POWER_ON + +/* Host communication */ +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 + +/* + * TODO(b/179648721): implement sensors + */ +#define CONFIG_TABLET_MODE +#define CONFIG_TABLET_MODE_SWITCH +#define CONFIG_GMR_TABLET_MODE + +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_HOST_EVENT + +/* LED */ +#define CONFIG_LED_COMMON + +/* Common charger defines */ +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 512 + +#define CONFIG_CMD_CHARGER_DUMP + +#define CONFIG_USB_CHARGER +#define CONFIG_BC12_DETECT_PI3USB9201 + +/* + * Don't allow the system to boot to S0 when the battery is low and unable to + * communicate on locked systems (which haven't PD negotiated) + */ +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 + +/* Common battery defines */ +#define CONFIG_BATTERY_SMART +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_PRESENT_CUSTOM +#define CONFIG_BATTERY_HW_PRESENT_CUSTOM +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_CMD_BATT_MFG_ACCESS + +/* Chipset config */ +#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 + +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_CPU_PROCHOT_ACTIVE_LOW +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_S0IX +#define CONFIG_POWER_SLEEP_FAILURE_DETECTION +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define CONFIG_LOW_POWER_IDLE + +#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST + +#define CONFIG_BOARD_HAS_RTC_RESET +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_HOSTCMD_AP_RESET + +/* Buttons / Switches */ +#define CONFIG_VOLUME_BUTTONS +#define CONFIG_SWITCH + +/* Common Keyboard Defines */ +#define CONFIG_CMD_KEYBOARD +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_KEYPAD +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#ifdef CONFIG_KEYBOARD_VIVALDI +#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 +#else +#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3 +#endif + +/* Thermal features */ +#define CONFIG_THROTTLE_AP +#define CONFIG_CHIPSET_CAN_THROTTLE + +#define CONFIG_PWM + +/* Enable I2C Support */ +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER + +/* EDP back-light control defines */ +#define CONFIG_BACKLIGHT_LID + +/* UART COMMAND */ +#define CONFIG_CMD_CHARGEN + +/* USB Type C and USB PD defines */ +/* Enable the new USB-C PD stack */ +#define CONFIG_USB_PD_TCPMV2 +#define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_PD_REV30 + +#define CONFIG_CMD_HCDEBUG +#define CONFIG_CMD_PPC_DUMP +#define CONFIG_CMD_TCPC_DUMP + +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_ALT_MODE_UFP +#define CONFIG_USB_PD_DISCHARGE_PPC +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TCPM_NCT38XX + +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_CMD_USB_PD_PE + +/* + * The PS8815 TCPC was found to require a 50ms delay to consistently work + * with non-PD chargers. Override the default low-power mode exit delay. + */ +#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) + +/* Enable USB3.2 DRD */ +#define CONFIG_USB_PD_USB32_DRD + +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_PD_VBUS_DETECT_TCPC + +#define CONFIG_USBC_PPC +/* Note - SN5S330 support automatically adds + * CONFIG_USBC_PPC_POLARITY + * CONFIG_USBC_PPC_SBU + * CONFIG_USBC_PPC_VCONN + */ +#define CONFIG_USBC_PPC_DEDICATED_INT + +#define CONFIG_USBC_SS_MUX +#define CONFIG_USB_MUX_VIRTUAL + +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP + +/* Enabling SOP* communication */ +#define CONFIG_CMD_USB_PD_CABLE +#define CONFIG_USB_PD_DECODE_SOP + +/* + * USB ID + * This is allocated specifically for Brya + * http://google3/hardware/standards/usb/ + */ +#define CONFIG_USB_PID 0x504F +/* Device version of product. */ +#define CONFIG_USB_BCD_DEV 0x0000 + +#ifndef __ASSEMBLER__ + +#include <stdbool.h> + +#include "common.h" +#include "baseboard_usbc_config.h" +#include "extpower.h" + +/** + * Configure run-time data structures and operation based on CBI data. This + * typically includes customization for changes in the BOARD_VERSION and + * FW_CONFIG fields in CBI. This routine is called from the baseboard after + * the CBI data has been initialized. + */ +__override_proto void board_cbi_init(void); + +/** + * Initialize the FW_CONFIG from CBI data. If the CBI data is not valid, set the + * FW_CONFIG to the board specific defaults. + */ +__override_proto void board_init_fw_config(void); + +/* + * Check battery disconnect state. + * This function will return if battery is initialized or not. + * @return true - initialized. false - not. + */ +__override_proto bool board_battery_is_initialized(void); + +/* + * Return the board revision number. + */ +uint8_t get_board_id(void); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h new file mode 100644 index 0000000000..1b16e5dd35 --- /dev/null +++ b/baseboard/dedede/baseboard.h @@ -0,0 +1,256 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Dedede board configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +/* + * By default, enable all console messages excepted HC, ACPI and event: + * The sensor stack is generating a lot of activity. + */ +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) + +/* + * Variant EC defines. Pick one: + * VARIANT_DEDEDE_EC_NPCX796FC + */ +#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || \ + defined(VARIANT_KEEBY_EC_NPCX797FC) + /* NPCX7 config */ + #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ + #define NPCX_TACH_SEL2 0 /* No tach. */ + + /* Internal SPI flash on NPCX7 */ + #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) + #define CONFIG_SPI_FLASH_REGS + #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ +#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ + defined(VARIANT_KEEBY_EC_IT8320) + /* IT83XX config */ + #define CONFIG_IT83XX_VCC_1P8V + /* I2C Bus Configuration */ + #define I2C_PORT_EEPROM IT83XX_I2C_CH_A + #define I2C_PORT_BATTERY IT83XX_I2C_CH_B + #define I2C_PORT_SENSOR IT83XX_I2C_CH_C + #define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E + #define I2C_PORT_USB_C0 IT83XX_I2C_CH_F + + #define I2C_ADDR_EEPROM_FLAGS 0x50 + + #define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */ + + #undef CONFIG_UART_TX_BUF_SIZE /* UART */ + #define CONFIG_UART_TX_BUF_SIZE 4096 +#else +#error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!" +#endif + +/* + * The key difference between Keeby and Dedede is that Keeby variants don't have + * a connection to H1 and therefore do not use EFS2. + */ +#if defined(VARIANT_KEEBY_EC_NPCX797FC) || defined(VARIANT_KEEBY_EC_IT8320) +#define KEEBY_VARIANT 1 +#else +#define KEEBY_VARIANT 0 +#endif + +/* + * Remapping of schematic GPIO names to common GPIO names expected (hardcoded) + * in the EC code base. + */ +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L +#define GPIO_EN_PP5000 GPIO_EN_PP5000_U +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#if !KEEBY_VARIANT +#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE +#endif +#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK +#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L +#if KEEBY_VARIANT +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#else +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#endif +#define GPIO_RSMRST_L_PGOOD GPIO_RSMRST_PWRGD_L +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD +#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_WP GPIO_EC_WP_OD +#define GMR_TABLET_MODE_GPIO_L GPIO_LID_360_L + +/* Common EC defines */ + +/* Work around double CR50 reset by waiting in initial power on. */ +#if !KEEBY_VARIANT +#define CONFIG_BOARD_RESET_AFTER_POWER_ON +#endif + +/* Optional console commands */ +#define CONFIG_CMD_CHARGER_DUMP + +/* Enable AP Reset command for TPM with old firmware version to detect it. */ +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_HOSTCMD_AP_RESET + +/* Enable i2ctrace command */ +#define CONFIG_I2C_DEBUG + +/* EC Modules */ +#define CONFIG_ADC +#define CONFIG_CRC8 +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_HOSTCMD_EVENTS +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER +#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_POWER_PP5000_CONTROL +#define CONFIG_VBOOT_HASH +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 +#if !KEEBY_VARIANT +#define CONFIG_VBOOT_EFS2 +#endif + +/* Battery */ +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATTERY_PRES_ODL +#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_BATTERY_SMART + +/* Buttons / Switches */ +#define CONFIG_SWITCH +#define CONFIG_VOLUME_BUTTONS +#define CONFIG_WP_ACTIVE_HIGH + +/* CBI */ +#define CONFIG_CBI_EEPROM +#define CONFIG_BOARD_VERSION_CBI + +/* Charger */ +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 256 +#define CONFIG_USB_CHARGER +#define CONFIG_TRICKLE_CHARGING + +/* Keyboard */ +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PROTOCOL_8042 + +/* Backlight */ +#define CONFIG_BACKLIGHT_LID +#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD + +/* LED */ +#define CONFIG_LED_COMMON + +/* Sensors */ +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT + +/* SoC */ +#define CONFIG_BOARD_HAS_RTC_RESET +#define CONFIG_CHIPSET_JASPERLAKE +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define CONFIG_POWER_S0IX +#define CONFIG_POWER_SLEEP_FAILURE_DETECTION +#define CONFIG_CPU_PROCHOT_ACTIVE_LOW + +/* USB Type-C */ +#define CONFIG_USB_MUX_PI3USB31532 +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_SS_MUX_DFP_ONLY +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP + +/* USB PD */ +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_DP_HPD_GPIO +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_REV30 +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TRY_SRC +/* #define CONFIG_USB_PD_VBUS_DETECT_CHARGER */ +#define CONFIG_USB_PD_VBUS_MEASURE_CHARGER +#define CONFIG_USB_PD_DECODE_SOP +#if KEEBY_VARIANT +#define CONFIG_USB_PID 0x5052 +#else +#define CONFIG_USB_PID 0x5042 +#endif +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_TCPMV2 +#define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_HOSTCMD_PD_CONTROL + +#if !KEEBY_VARIANT +/* UART COMMAND */ +#define CONFIG_CMD_CHARGEN +#endif + +/* Define typical operating power and max power. */ +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 45000 +#define PD_OPERATING_POWER_MW 15000 + +/* TODO(b:147314141): Verify these timings */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +#ifndef __ASSEMBLER__ + +#include "common.h" +#include "gpio_signal.h" + +/* Common enums */ +#if defined(VARIANT_DEDEDE_EC_NPCX796FC) +#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ + defined(VARIANT_KEEBY_EC_IT8320) + enum board_vcmp { + VCMP_SNS_PP3300_LOW, + VCMP_SNS_PP3300_HIGH, + VCMP_COUNT + }; +#endif + +/* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */ +void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal); + +/* Reset all TCPCs */ +void board_reset_pd_mcu(void); + +/* + * Bit to indicate if the PP3000_A rail's power is good. Will be updated by ADC + * interrupt. + */ +extern uint32_t pp3300_a_pgood; + +#endif /* !__ASSEMBLER__ */ +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/dragonegg/baseboard.h b/baseboard/dragonegg/baseboard.h index 0381b59097..c04200e218 100644 --- a/baseboard/dragonegg/baseboard.h +++ b/baseboard/dragonegg/baseboard.h @@ -41,7 +41,6 @@ #define CONFIG_CHARGER_BQ25710 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_V2 diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h index db79cadddc..d55bf581b9 100644 --- a/baseboard/grunt/baseboard.h +++ b/baseboard/grunt/baseboard.h @@ -159,13 +159,6 @@ #define PD_MAX_VOLTAGE_MV 20000 /* - * Minimum conditions to start AP and perform swsync. Note that when the - * charger is connected via USB-PD analog signaling, the boot will proceed - * regardless. - */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3 - -/* * Require PD negotiation to be complete when we are in a low-battery condition * prior to releasing depthcharge to the kernel. */ diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h new file mode 100644 index 0000000000..77e22c433b --- /dev/null +++ b/baseboard/guybrush/baseboard.h @@ -0,0 +1,368 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Guybrush baseboard configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +/* NPCX9 config */ +#define CONFIG_PORT80_4_BYTE +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ + +/* Optional features */ +#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT +#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ +#define CONFIG_LTO /* Link-Time Optimizations to reduce code size */ +#define CONFIG_I2C_DEBUG /* Print i2c traces */ +#define CONFIG_CMD_S5_TIMEOUT /* Allow a user-specified timeout to exit S5 */ + +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 4096 + +/* Vboot Config */ +#define CONFIG_CRC8 +#define CONFIG_VBOOT_EFS2 +#define CONFIG_VBOOT_HASH +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE + +/* CBI Config */ +#define CONFIG_CBI_EEPROM +#define CONFIG_BOARD_VERSION_CBI + +/* Power Config */ +#define CONFIG_CHIPSET_X86_RSMRST_DELAY +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_HIBERNATE_PSL +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_S0IX +#define CONFIG_POWER_SLEEP_FAILURE_DETECTION +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define G3_TO_PWRBTN_DELAY_MS 16 +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EN_PWR_A GPIO_EN_PWR_S5 +#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD +#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD +#define GPIO_S5_PGOOD GPIO_PG_PWR_S5 +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define SAFE_RESET_VBUS_DELAY_MS 900 +#define SAFE_RESET_VBUS_MV 5000 +/* + * On power-on, H1 releases the EC from reset but then quickly asserts and + * releases the reset a second time. This means the EC sees 2 resets: + * (1) power-on reset, (2) reset-pin reset. This config will + * allow the second reset to be treated as a power-on. + */ +#define CONFIG_BOARD_RESET_AFTER_POWER_ON + +/* Thermal Config */ +#define CONFIG_ADC +#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B +#define CONFIG_THROTTLE_AP +#define CONFIG_TEMP_SENSOR_SB_TSI +#define CONFIG_TEMP_SENSOR_TMP112 +#define CONFIG_THERMISTOR +#define CONFIG_CPU_PROCHOT_ACTIVE_LOW +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL + +/* Flash Config */ +/* See config_chip-npcx9.h for SPI flash configuration */ +#undef CONFIG_SPI_FLASH /* Don't enable external flash interface */ +#define GPIO_WP_L GPIO_EC_WP_L + +/* Host communication */ +#define CONFIG_CMD_CHARGEN +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT +#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L + +/* Chipset config */ +#define CONFIG_CHIPSET_CEZANNE +#define CONFIG_CHIPSET_CAN_THROTTLE +#define CONFIG_CHIPSET_RESET_HOOK + +/* Keyboard Config */ +#define CONFIG_KEYBOARD_BACKLIGHT +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#define CONFIG_KEYBOARD_VIVALDI +#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV + +/* Sensors */ +#define CONFIG_TABLET_MODE +#define CONFIG_GMR_TABLET_MODE +#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE + +/* Battery Config */ +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_BATTERY_SMART +#define CONFIG_BATTERY_V2 +#define CONFIG_BATTERY_COUNT 1 +#define CONFIG_HOSTCMD_BATTERY_V2 +#define CONFIG_BC12_DETECT_PI3USB9201 + +/* Charger Config */ +#define CONFIG_CHARGER +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_ISL9241 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 + +/* + * EC will boot AP to depthcharge if: (BAT >= 2%) || (AC >= 50W) + * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on + * Depthcharge to boot OS. + */ +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 + +/* + * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging + * but that feature of ISL9241 is broken (b/160287056) so we have to use + * CONFIG_CHARGE_RAMP_SW instead. + */ +#define CONFIG_CHARGE_RAMP_SW + +/* USB Type C and USB PD config */ +#define CONFIG_USB_PD_REV30 +#define CONFIG_USB_PD_TCPMV2 +#define CONFIG_USB_PD_DECODE_SOP +#define CONFIG_USB_DRP_ACC_TRYSRC +/* TODO: Enable TCPMv2 Fast Role Swap (FRS) */ +#define CONFIG_HOSTCMD_PD_CONTROL +#define CONFIG_CMD_TCPC_DUMP +#define CONFIG_USB_CHARGER +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_DISCHARGE_TCPC +#define CONFIG_USB_PD_DP_HPD_GPIO +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_USB_PD_TCPM_NCT38XX +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_VBUS_DETECT_TCPC +#define CONFIG_USBC_PPC +#define CONFIG_USBC_PPC_SBU +#define CONFIG_USBC_PPC_AOZ1380 +#define CONFIG_USBC_RETIMER_PI3HDX1204 +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_SS_MUX_DFP_ONLY +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP +#define CONFIG_USB_MUX_ANX7451 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USBC_PPC_NX20P3483 +#define CONFIG_USBC_RETIMER_PS8811 +#define CONFIG_USBC_RETIMER_PS8818 +#define CONFIG_USBC_RETIMER_ANX7451 +#define CONFIG_USB_MUX_RUNTIME_CONFIG +#define CONFIG_USB_MUX_AMD_FP6 + +#define GPIO_USB_C0_DP_HPD GPIO_USB_C0_HPD +#define GPIO_USB_C1_DP_HPD GPIO_USB_C1_HPD + +#define CONFIG_IO_EXPANDER +#define CONFIG_IO_EXPANDER_NCT38XX +#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT + +/* TODO(b/176988382): Tune values for guybrush */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ + +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 +/* Max Power = 100 W */ +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) + +/* USB-A config */ +#define USB_PORT_COUNT USBA_PORT_COUNT +#define CONFIG_USB_PORT_POWER_SMART +#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY +#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP +#define CONFIG_USB_PORT_POWER_SMART_INVERTED + +#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_LIMIT_SDP +#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_LIMIT_SDP_DB + +/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ +#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 + +/* + * USB ID - This is allocated specifically for Guybrush + */ +#define CONFIG_USB_PID 0x504D + +/* BC 1.2 */ +/* + * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current + * until voltage drops to 4.5V. Don't go lower than this to be kind to the + * charger (see b/67964166). + */ +#define BC12_MIN_VOLTAGE 4500 + +/* I2C Bus Configuration */ +#define CONFIG_I2C +#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED +#define CONFIG_I2C_CONTROLLER +#define CONFIG_I2C_UPDATE_IF_CHANGED +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT4_1 +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +/* Volume Button Config */ +#define CONFIG_VOLUME_BUTTONS +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL + +/* Fan Config */ +#define CONFIG_FANS FAN_CH_COUNT +/* TODO: Set CONFIG_FAN_INIT_SPEED, defaults to 100 */ + +/* LED Config */ +#define CONFIG_PWM +#define CONFIG_PWM_KBLIGHT + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +/* Power input signals */ +enum power_signal { + X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ + X86_SLP_S3_N, /* SOC -> SLP_S3_L */ + X86_SLP_S5_N, /* SOC -> SLP_S5_L */ + + X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ + X86_S5_PGOOD, /* PMIC -> S5_PWROK */ + + /* Number of X86 signals */ + POWER_SIGNAL_COUNT, +}; + +/* USB-C ports */ +enum usbc_port { + USBC_PORT_C0 = 0, + USBC_PORT_C1, + USBC_PORT_COUNT +}; + +/* USB-A ports */ +enum usba_port { + USBA_PORT_A0 = 0, + USBA_PORT_A1, + USBA_PORT_COUNT +}; + +/* ADC Channels */ +enum adc_channel { + ADC_TEMP_SENSOR_SOC = 0, + ADC_TEMP_SENSOR_CHARGER, + ADC_TEMP_SENSOR_MEMORY, + ADC_CORE_IMON1, + ADC_SOC_IMON2, + ADC_CH_COUNT +}; + +/* TMP112 sensors */ +enum tmp112_sensor { + TMP112_SOC, /* Note: MUST match ADC SOC as they share an idx value */ + TMP112_AMB, + TMP112_COUNT, +}; + +/* Temp Sensors */ +enum temp_sensor_id { + TEMP_SENSOR_SOC = 0, + TEMP_SENSOR_CHARGER, + TEMP_SENSOR_MEMORY, + TEMP_SENSOR_CPU, + TEMP_SENSOR_AMBIENT, + TEMP_SENSOR_COUNT +}; + +enum sensor_id { + BASE_ACCEL = 0, + BASE_GYRO, + SENSOR_COUNT, +}; + +/* PWM Channels */ +enum pwm_channel { + PWM_CH_FAN = 0, + PWM_CH_KBLIGHT, + PWM_CH_LED_CHRG, + PWM_CH_LED_FULL, + PWM_CH_COUNT +}; + +/* Fan Channels */ +enum fan_channel { + FAN_CH_0 = 0, + /* Number of FAN channels */ + FAN_CH_COUNT, +}; +enum mft_channel { + MFT_CH_0 = 0, + /* Number of MFT channels */ + MFT_CH_COUNT, +}; + +/* Common definition for the USB PD interrupt handlers. */ +void tcpc_alert_event(enum gpio_signal signal); +void bc12_interrupt(enum gpio_signal signal); +void ppc_interrupt(enum gpio_signal signal); +void sbu_fault_interrupt(enum ioex_signal signal); + +void baseboard_en_pwr_pcore_s0(enum gpio_signal signal); +void baseboard_en_pwr_s0(enum gpio_signal signal); + +int board_get_soc_temp(int idx, int *temp_k); + +/* CBI utility functions */ +uint32_t get_sku_id(void); +uint32_t get_board_version(void); +uint32_t get_fw_config(void); +/* Board callback after CBI has been initialized */ +__overridable void board_cbi_init(void); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h new file mode 100644 index 0000000000..d57de6e3cd --- /dev/null +++ b/baseboard/intelrvp/baseboard.h @@ -0,0 +1,275 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel BASEBOARD-RVP board-specific configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +#include "compiler.h" +#include "stdbool.h" + +#ifdef VARIANT_INTELRVP_EC_IT8320 + #include "ite_ec.h" +#elif defined(VARIANT_INTELRVP_EC_MCHP) + #include "mchp_ec.h" +#elif defined(VARIANT_INTELRVP_EC_NPCX) + #include "npcx_ec.h" +#else + #error "Define EC chip variant" +#endif + +/* + * Allow dangerous commands. + * TODO: Remove this config before production. + */ +#define CONFIG_SYSTEM_UNLOCKED + +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#undef CONFIG_HOSTCMD_DEBUG_MODE + +/* + * By default, enable all console messages excepted HC, ACPI and event: + * The sensor stack is generating a lot of activity. + */ +#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF + +/* EC console commands */ +#define CONFIG_CMD_CHARGER_DUMP +#define CONFIG_CMD_KEYBOARD +#define CONFIG_CMD_USB_PD_CABLE +#define CONFIG_CMD_USB_PD_PE + +/* Host commands */ +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_HOSTCMD_AP_RESET +#define CONFIG_HOSTCMD_PD_CONTROL + +/* Port80 display */ +#define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY + +/* Battery */ +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_BATTERY_SMART + +/* Charger */ +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_SENSE_RESISTOR 5 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_TRICKLE_CHARGING + +/* + * Don't allow the system to boot to S0 when the battery is low and unable to + * communicate on locked systems (which haven't PD negotiated) + */ +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 + +/* Keyboard */ +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 + +/* UART */ +#define CONFIG_LOW_POWER_IDLE + +/* USB-A config */ + +/* BC1.2 config */ +#ifdef HAS_TASK_USB_CHG_P0 + #define CONFIG_CHARGE_RAMP_HW +#endif + +/* Enable USB-PD REV 3.0 */ +#define CONFIG_USB_PD_REV30 +#define CONFIG_USB_PID 0x8086 + +/* USB PD config */ +#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1) + #define CONFIG_USB_PD_TCPMV1 + #define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 +#else + #define CONFIG_USB_DRP_ACC_TRYSRC + #define CONFIG_USB_PD_DECODE_SOP + #define CONFIG_USB_PD_TCPMV2 + #define CONFIG_USB_PD_TCPM_MUX +#endif +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_POWER_DELIVERY + +/* USB MUX */ +#ifdef CONFIG_USB_MUX_VIRTUAL + #define CONFIG_HOSTCMD_LOCATE_CHIP +#endif +#define CONFIG_USBC_SS_MUX + +/* SoC / PCH */ +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 +#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_HOST_EVENT +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_S0IX +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE + +/* EC */ +#define CONFIG_BOARD_VERSION_CUSTOM +#define CONFIG_LED_COMMON +#define CONFIG_LID_SWITCH +#define CONFIG_VOLUME_BUTTONS +#define CONFIG_WP_ALWAYS + +/* Tablet mode */ +#define CONFIG_TABLET_MODE +#define CONFIG_GMR_TABLET_MODE + +/* Verified boot */ +#define CONFIG_CRC8 +#define CONFIG_SHA256_UNROLLED +#define CONFIG_VBOOT_HASH + +/* + * Enable 1 slot of secure temporary storage to support + * suspend/resume with read/write memory training. + */ +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 + +/* Temperature sensor */ +#ifdef CONFIG_TEMP_SENSOR + #define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B + #define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A + #define CONFIG_THERMISTOR + #define CONFIG_THROTTLE_AP +#ifdef CONFIG_PECI + #define CONFIG_PECI_COMMON +#endif /* CONFIG_PECI */ +#endif /* CONFIG_TEMP_SENSOR */ + +/* I2C ports */ +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER + +/* EC exclude modules */ + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "module_id.h" +#include "registers.h" + +FORWARD_DECLARE_ENUM(tcpc_rp_value); + +/* PWM channels */ +enum pwm_channel { + PWM_CH_FAN, + PWM_CH_COUNT +}; + +/* FAN channels */ +enum fan_channel { + FAN_CH_0, + FAN_CH_COUNT, +}; + +/* ADC channels */ +enum adc_channel { + ADC_TEMP_SNS_AMBIENT, + ADC_TEMP_SNS_DDR, + ADC_TEMP_SNS_SKIN, + ADC_TEMP_SNS_VR, + ADC_CH_COUNT, +}; + +/* Temperature sensors */ +enum temp_sensor_id { + TEMP_SNS_AMBIENT, + TEMP_SNS_BATTERY, + TEMP_SNS_DDR, +#ifdef CONFIG_PECI + TEMP_SNS_PECI, +#endif + TEMP_SNS_SKIN, + TEMP_SNS_VR, + TEMP_SENSOR_COUNT, +}; + +/* TODO(b:132652892): Verify the below numbers. */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +/* Define typical operating power */ +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000) +#define DC_JACK_MAX_VOLTAGE_MV 19000 + +/* TCPC gpios */ +struct tcpc_gpio_t { + enum gpio_signal pin; + uint8_t pin_pol; +}; + +/* VCONN gpios */ +struct vconn_gpio_t { + enum gpio_signal cc1_pin; + enum gpio_signal cc2_pin; + uint8_t pin_pol; +}; + +struct tcpc_gpio_config_t { + /* VBUS interrput */ + struct tcpc_gpio_t vbus; + /* Source enable */ + struct tcpc_gpio_t src; + /* Sink enable */ + struct tcpc_gpio_t snk; +#if defined(CONFIG_USBC_VCONN) && defined(CHIP_FAMILY_IT83XX) + /* Enable VCONN */ + struct vconn_gpio_t vconn; +#endif + /* Enable source ILIM */ + struct tcpc_gpio_t src_ilim; +}; +extern const struct tcpc_gpio_config_t tcpc_gpios[]; + +struct tcpc_aic_gpio_config_t { + /* TCPC interrupt */ + enum gpio_signal tcpc_alert; + /* PPC interrupt */ + enum gpio_signal ppc_alert; + /* PPC interrupt handler */ + void (*ppc_intr_handler)(int port); +}; +extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[]; + +void board_charging_enable(int port, int enable); +void board_vbus_enable(int port, int enable); +void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp); +int ioexpander_read_intelrvp_version(int *port0, int *port1); +void board_dc_jack_interrupt(enum gpio_signal signal); +void tcpc_alert_event(enum gpio_signal signal); +bool is_typec_port(int port); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/kukui/baseboard.h b/baseboard/kukui/baseboard.h new file mode 100644 index 0000000000..9ba11111e8 --- /dev/null +++ b/baseboard/kukui/baseboard.h @@ -0,0 +1,330 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Kukui board configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +/* + * Variant battery defines, pick one: + * VARIANT_KUKUI_BATTERY_MAX17055 + * VARIANT_KUKUI_BATTERY_MM8013 + * VARIANT_KUKUI_BATTERY_BQ27541 + * VARIANT_KUKUI_BATTERY_SMART + */ +#if defined(VARIANT_KUKUI_BATTERY_MAX17055) +#define CONFIG_BATTERY_MAX17055 +#define CONFIG_BATTERY_MAX17055_ALERT +#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ +#elif defined(VARIANT_KUKUI_BATTERY_MM8013) +#define CONFIG_BATTERY_MM8013 +#elif defined(VARIANT_KUKUI_BATTERY_BQ27541) +#define CONFIG_BATTERY_BQ27541 +#elif defined(VARIANT_KUKUI_BATTERY_SMART) +#define CONFIG_BATTERY_SMART +#define CONFIG_BATTERY_FUEL_GAUGE +#else +#error Must define a VARIANT_KUKUI_BATTERY +#endif /* VARIANT_KUKUI_BATTERY */ + +/* + * Variant charger defines, pick one: + * VARIANT_KUKUI_CHARGER_MT6370 + * VARIANT_KUKUI_CHARGER_ISL9238 + */ +#if defined(VARIANT_KUKUI_CHARGER_MT6370) +#define CONFIG_CHARGER_MT6370 +#define CONFIG_CHARGER_MT6370_BC12_GPIO +#define CONFIG_CHARGE_RAMP_HW +#define CONFIG_CHARGER_OTG +#define CONFIG_CHARGER_PROFILE_OVERRIDE +#define CONFIG_USB_PD_TCPM_MT6370 +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_DISCHARGE_TCPC +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE + +/* TCPC MT6370 */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +/* + * The Maximum input voltage is 13.5V, need another 5% tolerance. + * 12.85V * 1.05 = 13.5V + */ +#define PD_MAX_VOLTAGE_MV 12850 +#define CONFIG_USB_PD_PREFER_MV +#elif defined(VARIANT_KUKUI_CHARGER_ISL9238) +#define CONFIG_CHARGER_ISL9238C +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* BOARD_RS1 */ +#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* BOARD_RS2 */ +#define CONFIG_CHARGER_OTG +#define CONFIG_CHARGE_RAMP_HW + +/* TCPC FUSB302 */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +/* b/2230219: 15V has better charging performance than 20V */ +#define PD_MAX_VOLTAGE_MV 15000 +#else +#error Must define a VARIANT_KUKUI_CHARGER +#endif /* VARIANT_KUKUI_CHARGER */ + +/* + * Variant pogo defines, if pick, VARIANT_KUKUI_POGO_KEYBOARD is mandatory + * VARIANT_KUKUI_POGO_KEYBOARD + * VARIANT_KUKUI_POGO_DOCK + */ +#ifdef VARIANT_KUKUI_POGO_DOCK +#ifndef VARIANT_KUKUI_POGO_KEYBOARD +#error VARIANT_KUKUI_POGO_KEYBOARD is mandatory if use dock +#endif /* !VARIANT_KUKUI_POGO_KEYBOARD */ +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 +#define DEDICATED_CHARGE_PORT 1 +#endif /* VARIANT_KUKUI_POGO_DOCK */ + +#ifdef VARIANT_KUKUI_POGO_KEYBOARD +#define CONFIG_DETACHABLE_BASE +#define CONFIG_BASE_ATTACHED_SWITCH +#endif + +/* define this if the board is jacuzzi family */ +#ifdef VARIANT_KUKUI_JACUZZI +#define CONFIG_HOSTCMD_AP_SET_SKUID +/* + * IT81202 based boards are variant of jacuzzi and I/O expander isn't required + * on them. + */ +#ifdef VARIANT_KUKUI_EC_STM32F098 +#define CONFIG_IO_EXPANDER +#define CONFIG_IO_EXPANDER_IT8801 +#define CONFIG_IO_EXPANDER_PORT_COUNT 1 +#define CONFIG_KEYBOARD_NOT_RAW +#define CONFIG_KEYBOARD_BOARD_CONFIG +#endif +#define CONFIG_KEYBOARD_COL2_INVERTED + +#define CONFIG_GMR_TABLET_MODE +#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L +#define CONFIG_TABLET_MODE +#define CONFIG_TABLET_MODE_SWITCH + +#define PD_OPERATING_POWER_MW 30000 +#endif /* VARIANT_KUKUI_JACUZZI */ + +/* + * Define this flag if board controls dp mux via gpio pins USB_C0_DP_OE_L and + * USB_C0_DP_POLARITY. + * + * board must provide function board_set_dp_mux_control(output_enable, polarity) + * + * #define VARIANT_KUKUI_DP_MUX_GPIO + */ + +/* Optional modules */ +#define CONFIG_ADC +#undef CONFIG_ADC_WATCHDOG +#define CONFIG_CHIPSET_MT8183 +#define CONFIG_CMD_ACCELS +#define CONFIG_EMULATED_SYSRQ +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER +#define CONFIG_I2C_VIRTUAL_BATTERY +#define CONFIG_I2C_PASSTHRU_RESTRICTED +#define CONFIG_LED_COMMON +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_POWER_COMMON +#define CONFIG_SPI +#define CONFIG_SWITCH + +#ifdef SECTION_IS_RO +#undef CONFIG_SYSTEM_UNLOCKED /* Disabled in RO to save space */ +#else +#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ +#endif + +/* Bootblock */ +#ifdef SECTION_IS_RO +#define CONFIG_BOOTBLOCK + +#define EMMC_SPI_PORT 2 +#endif + +/* Optional features */ +#define CONFIG_BOARD_PRE_INIT +#define CONFIG_BOARD_VERSION_CUSTOM +#define CONFIG_BUTTON_TRIGGERED_RECOVERY +#define CONFIG_CHARGER_ILIM_PIN_DISABLED +#define CONFIG_FORCE_CONSOLE_RESUME +#define CONFIG_HOST_COMMAND_STATUS +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_PRESERVE_LOGS + +/* Required for FAFT */ +#define CONFIG_CMD_BUTTON +#define CONFIG_CMD_CHARGEN + +/* By default, set hcdebug to off */ +#undef CONFIG_HOSTCMD_DEBUG_MODE +#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF + +#define CONFIG_LTO +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_IGNORE_LID +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define CONFIG_SOFTWARE_PANIC +#define CONFIG_VBOOT_HASH + +#define CONFIG_CHARGER +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 2 +#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000 +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM +#define CONFIG_USB_CHARGER + +/* Increase tx buffer size, as we'd like to stream EC log to AP. */ +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 4096 + +#define GPIO_LID_OPEN GPIO_HALL_INT_L + +#ifndef VARIANT_KUKUI_NO_SENSORS +#define CONFIG_ACCEL_FIFO +/* FIFO size is in power of 2. */ +#define CONFIG_ACCEL_FIFO_SIZE 256 +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) +#endif /* VARIANT_KUKUI_NO_SENSORS */ + +#ifndef VARIANT_KUKUI_TABLET_PWRBTN +#define POWERBTN_BOOT_DELAY 0 +#endif + +/* USB PD config */ +#define CONFIG_CHARGE_MANAGER +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_PORT_MAX_COUNT 1 +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_5V_EN_CUSTOM +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP +#define CONFIG_USB_PD_COMM_LOCKED + +#define CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_PRESENT_CUSTOM +#define CONFIG_BATTERY_REVIVE_DISCONNECT + +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#ifdef BOARD_KODAMA +#define PD_MAX_CURRENT_MA 2000 +#else +#define PD_MAX_CURRENT_MA 3000 +#endif + +/* Optional for testing */ +#undef CONFIG_PECI +#undef CONFIG_PSTORE + +#define CONFIG_TASK_PROFILING +#define CONFIG_MKBP_USE_GPIO + +/* + * Variant EC defines. Pick one: + * VARIANT_KUKUI_EC_STM32F098 + * VARIANT_KUKUI_EC_IT81202 + */ +#if defined(VARIANT_KUKUI_EC_STM32F098) +/* Timer selection */ +#define TIM_CLOCK32 2 +#define TIM_WATCHDOG 7 + +/* 48 MHz SYSCLK clock frequency */ +#define CPU_CLOCK 48000000 + +#undef CONFIG_HIBERNATE +#define CONFIG_SPI_CONTROLLER +#define CONFIG_STM_HWTIMER32 +#define CONFIG_WATCHDOG_HELP +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 1 +#define CONFIG_UART_RX_DMA + +/* This option is limited to TCPMv1 */ +#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 +/* STM32F098 based boards use TCPMv1 */ +#define CONFIG_USB_PD_TCPMV1 +#define CONFIG_USB_PD_VBUS_DETECT_TCPC + +/* Modules we want to exclude */ +#undef CONFIG_CMD_BATTFAKE +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_HASH +#undef CONFIG_CMD_MD +#undef CONFIG_CMD_POWERINDEBUG +#undef CONFIG_CMD_TIMERINFO + +/* save space at RO image */ +#ifdef SECTION_IS_RO +#undef CONFIG_CMD_APTHROTTLE +#undef CONFIG_CMD_CRASH +#undef CONFIG_CMD_HCDEBUG +#undef CONFIG_CMD_IDLE_STATS +#undef CONFIG_CMD_MMAPINFO +#undef CONFIG_CMD_PWR_AVG +#undef CONFIG_CMD_REGULATOR +#undef CONFIG_CMD_RW +#undef CONFIG_CMD_SHMEM +#undef CONFIG_CMD_SLEEPMASK +#undef CONFIG_CMD_SLEEPMASK_SET +#undef CONFIG_CMD_SYSLOCK +#undef CONFIG_HOSTCMD_FLASHPD +#undef CONFIG_HOSTCMD_RWHASHPD +#undef CONFIG_CONSOLE_CMDHELP + +#undef CONFIG_HOSTCMD_GET_UPTIME_INFO +#undef CONFIG_CMD_AP_RESET_LOG +#undef CONFIG_CMD_I2C_SCAN +#undef CONFIG_CMD_I2C_XFER + +/* free flash space */ +#undef CONFIG_USB_PD_DEBUG_LEVEL +#define CONFIG_USB_PD_DEBUG_LEVEL 0 +#undef CONFIG_USB_PD_LOGGING +#define CONFIG_COMMON_GPIO_SHORTNAMES +/* Exclude PD state names from RO image to save space */ +#undef CONFIG_USB_PD_TCPMV1_DEBUG +#endif +#elif defined(VARIANT_KUKUI_EC_IT81202) +#define CONFIG_IT83XX_HARD_RESET_BY_GPG1 +#define CONFIG_IT83XX_VCC_1P8V + +/* IT81202 based boards use TCPMv2 */ +#define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_PD_DECODE_SOP +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 +#define CONFIG_USB_PD_TCPMV2 +#else +#error "Must define a VARIANT_KUKUI_EC_XXX!" +#endif + +#ifndef __ASSEMBLER__ +#ifdef VARIANT_KUKUI_DP_MUX_GPIO +void board_set_dp_mux_control(int output_enable, int polarity); +#endif /* VARIANT_KUKUI_DP_MUX_GPIO */ + +/* If POGO pin is providing power. */ +int kukui_pogo_extpower_present(void); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index 63e94571da..57e02261a8 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -121,7 +121,6 @@ #define CONFIG_CHARGER #define CONFIG_CHARGER_V2 #define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_USB_CHARGER diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h new file mode 100644 index 0000000000..398c9cf912 --- /dev/null +++ b/baseboard/trogdor/baseboard.h @@ -0,0 +1,216 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Trogdor baseboard configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +/* + * By default, enable all console messages excepted event and HC: + * The sensor stack is generating a lot of activity. + * They can be enabled through the console command 'chan'. + */ +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) + +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ + +/* Internal SPI flash on NPCX7 */ +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ + +/* EC Modules */ +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER +#define CONFIG_I2C_VIRTUAL_BATTERY +#define CONFIG_I2C_PASSTHRU_RESTRICTED +#define CONFIG_LED_COMMON +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_ADC +#define CONFIG_BACKLIGHT_LID +#define CONFIG_FPU +#define CONFIG_PWM +#define CONFIG_PWM_DISPLIGHT + +#define CONFIG_VBOOT_HASH + +#undef CONFIG_PECI + +#define CONFIG_HOSTCMD_SPS +#define CONFIG_HOST_COMMAND_STATUS +#define CONFIG_HOSTCMD_SECTION_SORTED +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_MKBP_USE_GPIO + +#define CONFIG_BOARD_VERSION_GPIO +#define CONFIG_POWER_BUTTON +#define CONFIG_VOLUME_BUTTONS +#define CONFIG_EMULATED_SYSRQ +#define CONFIG_CMD_BUTTON +#define CONFIG_SWITCH +#define CONFIG_LID_SWITCH +#define CONFIG_EXTPOWER_GPIO + +/* + * On power-on, H1 releases the EC from reset but then quickly asserts and + * releases the reset a second time. This means the EC sees 2 resets: + * (1) power-on reset, (2) reset-pin reset. This config will + * allow the second reset to be treated as a power-on. + */ +#define CONFIG_BOARD_RESET_AFTER_POWER_ON + +/* Increase console output buffer since we have the RAM available. */ +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 4096 + +/* Battery */ +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL +#define CONFIG_BATTERY_SMART + +/* Charger */ +#define CONFIG_CHARGER +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER_ISL9238 +#define CONFIG_CHARGER_PROFILE_OVERRIDE +#define CONFIG_CHARGE_RAMP_HW +#define CONFIG_USB_CHARGER +#define CONFIG_CMD_CHARGER_ADC_AMON_BMON +#define CONFIG_CHARGER_PSYS +#define CONFIG_CHARGER_PSYS_READ +#define CONFIG_CHARGER_DISCHARGE_ON_AC + +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 10000 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 + +/* + * USB ID + * + * This is allocated specifically for Trogdor + * http://google3/hardware/standards/usb/ + */ +#define CONFIG_USB_PID 0x5043 + +/* USB */ +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_TCPMV2 +#define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_PD_DECODE_SOP +#define CONFIG_HOSTCMD_PD_CONTROL +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_DISCHARGE_PPC +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_CMD_TCPC_DUMP +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_PD_VBUS_DETECT_TCPC +#define CONFIG_USB_PD_5V_EN_CUSTOM +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_SS_MUX_DFP_ONLY +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP + +/* RTC */ +#define CONFIG_CMD_RTC +#define CONFIG_HOSTCMD_RTC + +/* Sensors */ +/* Enable sensor fifo, must also define the _SIZE and _THRES */ +#define CONFIG_ACCEL_FIFO +/* FIFO size is a power of 2. */ +#define CONFIG_ACCEL_FIFO_SIZE 256 +/* Depends on how fast the AP boots and typical ODRs. */ +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) +#define CONFIG_CMD_ACCELS +#define CONFIG_CMD_ACCEL_INFO + +/* PD */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +#define PD_OPERATING_POWER_MW 10000 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + +/* Chipset */ +#define CONFIG_CHIPSET_SC7180 +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_CHIPSET_RESUME_INIT_HOOK +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_PP5000_CONTROL +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define CONFIG_POWER_SLEEP_FAILURE_DETECTION +#define CONFIG_CMD_AP_RESET_LOG + +/* + * Macros for GPIO signals used in common code that don't match the + * schematic names. Signal names in gpio.inc match the schematic and are + * then redefined here to so it's more clear which signal is being used for + * which purpose. + */ +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_LID_OPEN GPIO_LID_OPEN_EC +#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L +#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 +#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 +#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV + +/* I2C Ports */ +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_WLC NPCX_I2C_PORT3_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 + +/* UART */ +#define CONFIG_CMD_CHARGEN + +/* Define the host events which are allowed to wake AP up from S3 */ +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE) + +/* And the MKBP events */ +#ifdef HAS_TASK_KEYSCAN +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ + BIT(EC_MKBP_EVENT_HOST_EVENT) | \ + BIT(EC_MKBP_EVENT_SENSOR_FIFO)) +#else +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ + BIT(EC_MKBP_EVENT_SENSOR_FIFO)) +#endif + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h new file mode 100644 index 0000000000..4ea3d81676 --- /dev/null +++ b/baseboard/volteer/baseboard.h @@ -0,0 +1,285 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Volteer baseboard configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +#include <stdbool.h> + +/* + * By default, enable all console messages excepted HC + */ +#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) + +/* NPCX7 config */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +/* Internal SPI flash on NPCX796FC is 512 kB */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ + +/* Allow objects to be linked into a flash resident section */ +#define CONFIG_CHIP_INIT_ROM_REGION + +/* EC Defines */ +#define CONFIG_LTO +#define CONFIG_BOARD_VERSION_CBI +#define CONFIG_CRC8 +#define CONFIG_CBI_EEPROM +#define CONFIG_DPTF +#define CONFIG_FPU +#define CONFIG_HIBERNATE_PSL +#define CONFIG_PWM +#define CONFIG_VBOOT_HASH +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 +#define CONFIG_VOLUME_BUTTONS +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_BOARD_RESET_AFTER_POWER_ON + +/* Host communication */ +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 + +/* Chipset config */ +#define CONFIG_CHIPSET_TIGERLAKE +#define CONFIG_CHIPSET_PP3300_RAIL_FIRST +#define CONFIG_CHIPSET_SLP_S3_L_OVERRIDE +#define CONFIG_CHIPSET_X86_RSMRST_DELAY +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_CPU_PROCHOT_ACTIVE_LOW +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_S0IX +#define CONFIG_POWER_SLEEP_FAILURE_DETECTION +#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define CONFIG_BOARD_HAS_RTC_RESET + +/* Common Keyboard Defines */ +#define CONFIG_CMD_KEYBOARD +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_KEYPAD +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 +#define CONFIG_PWM_KBLIGHT + +/* Sensors */ +#define CONFIG_TABLET_MODE +#define CONFIG_GMR_TABLET_MODE + +#define CONFIG_MKBP_EVENT +#define CONFIG_MKBP_USE_GPIO +#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT +#define CONFIG_ACCEL_INTERRUPTS + +/* Enable sensor fifo, must also define the _SIZE and _THRES */ +#define CONFIG_ACCEL_FIFO +/* FIFO size is in power of 2. */ +#define CONFIG_ACCEL_FIFO_SIZE 256 +/* Depends on how fast the AP boots and typical ODRs */ +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) + +/* Sensor console commands */ +#define CONFIG_CMD_ACCELS +#define CONFIG_CMD_ACCEL_INFO + +/* Thermal features */ +#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_TEMP_SENSOR +#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PG_EC_DSW_PWROK +#define CONFIG_THERMISTOR +#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B +#define CONFIG_THROTTLE_AP +#define CONFIG_CHIPSET_CAN_THROTTLE + +/* Common charger defines */ +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 512 + +/* + * Hardware based charge ramp is broken in the ISL9241 (b/169350714). + */ +#define CONFIG_CHARGE_RAMP_SW +#define CONFIG_CHARGER_ISL9241 +/* Setting ISL9241 Register Control1 switching frequency to 724kHz. */ +#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ + +#define CONFIG_USB_CHARGER +#define CONFIG_BC12_DETECT_PI3USB9201 + +/* + * Don't allow the system to boot to S0 when the battery is low and unable to + * communicate on locked systems (which haven't PD negotiated) + */ +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 + +/* Common battery defines */ +#define CONFIG_BATTERY_SMART +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_PRESENT_CUSTOM +#define CONFIG_BATTERY_HW_PRESENT_CUSTOM +#define CONFIG_BATTERY_REVIVE_DISCONNECT + +/* Common LED defines */ +#define CONFIG_LED_COMMON + +/* EDP back-light control defines */ +#define CONFIG_BACKLIGHT_LID +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN + +/* USB Type C and USB PD defines */ +/* Enable the new USB-C PD stack */ +#define CONFIG_USB_PD_TCPMV2 +#define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_PD_REV30 + +/* + * TODO(b/158572770): TCPMv2: Conserve flash space + * Add these console commands as flash space permits. + */ +#undef CONFIG_CMD_HCDEBUG +#undef CONFIG_CMD_ACCELS +#undef CONFIG_CMD_ACCEL_INFO +#undef CONFIG_CMD_ACCELSPOOF +#undef CONFIG_CMD_PPC_DUMP + +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_ALT_MODE_UFP +#define CONFIG_USB_PD_DISCHARGE_PPC +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TCPM_RT1715 +#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */ +#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */ +#define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_CMD_USB_PD_PE + +/* + * Because of the CSE Lite, an extra cold AP reset is needed, and older cr50 + * firmware will not be able to detect it because of updated cr50 pin straps. + * Therefore, the AP will require the EC to reset it so that the proper reset + * signal will be read and verstage can execute again. + */ +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_HOSTCMD_AP_RESET + +/* + * The PS8815 TCPC was found to require a 50ms delay to consistently work + * with non-PD chargers. Override the default low-power mode exit delay. + */ +#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) + +/* Enable USB3.2 DRD */ +#define CONFIG_USB_PD_USB32_DRD + +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_PD_VBUS_DETECT_TCPC + +#define CONFIG_USB_MUX_RUNTIME_CONFIG + +#define CONFIG_USBC_PPC +/* Note - SN5S330 support automatically adds + * CONFIG_USBC_PPC_POLARITY + * CONFIG_USBC_PPC_SBU + * CONFIG_USBC_PPC_VCONN + */ +#define CONFIG_USBC_PPC_DEDICATED_INT + +#define CONFIG_USBC_SS_MUX +#define CONFIG_USB_MUX_VIRTUAL + +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP + +/* Enabling SOP* communication */ +#define CONFIG_CMD_USB_PD_CABLE +#define CONFIG_USB_PD_DECODE_SOP + +/* UART COMMAND */ +#define CONFIG_CMD_CHARGEN + +/* + * USB ID + * This is allocated specifically for Volteer + * http://google3/hardware/standards/usb/ + */ +#define CONFIG_USB_PID 0x503E +/* Device version of product. */ +#define CONFIG_USB_BCD_DEV 0x0000 + +/* Retimer */ +#define CONFIG_USBC_RETIMER_INTEL_BB +#define CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG +#define CONFIG_USBC_RETIMER_FW_UPDATE + +/* Enable volume button command in EC console */ +#define CONFIG_CMD_BUTTON + +/* Enable volume button in ectool */ +#define CONFIG_HOSTCMD_BUTTON + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "common.h" +#include "baseboard_usbc_config.h" +#include "cbi.h" + +enum adc_channel { + ADC_TEMP_SENSOR_1_CHARGER, + ADC_TEMP_SENSOR_2_PP3300_REGULATOR, + ADC_TEMP_SENSOR_3_DDR_SOC, + ADC_TEMP_SENSOR_4_FAN, + ADC_CH_COUNT +}; + +enum fan_channel { + FAN_CH_0 = 0, + /* Number of FAN channels */ + FAN_CH_COUNT, +}; + +enum mft_channel { + MFT_CH_0 = 0, + /* Number of MFT channels */ + MFT_CH_COUNT, +}; + +enum temp_sensor_id { + TEMP_SENSOR_1_CHARGER, + TEMP_SENSOR_2_PP3300_REGULATOR, + TEMP_SENSOR_3_DDR_SOC, + TEMP_SENSOR_4_FAN, + TEMP_SENSOR_COUNT +}; + +/* + * Check battery disconnect state. + * This function will return if battery is initialized or not. + * @return true - initialized. false - not. + */ +__override_proto bool board_battery_is_initialized(void); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h new file mode 100644 index 0000000000..60db6e1cb2 --- /dev/null +++ b/baseboard/zork/baseboard.h @@ -0,0 +1,368 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Zork baseboard configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +#if (defined(VARIANT_ZORK_TREMBYLE) \ + + defined(VARIANT_ZORK_DALBOZ)) != 1 +#error Must choose VARIANT_ZORK_TREMBYLE or VARIANT_ZORK_DALBOZ +#endif + +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ + +/* Internal SPI flash on NPCX7 */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */ + +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC))) + +/* + * Enable 1 slot of secure temporary storage to support + * suspend/resume with read/write memory training. + */ +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 + +#define CONFIG_ADC +#define CONFIG_BACKLIGHT_LID +#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_CPU_PROCHOT_ACTIVE_LOW +#define CONFIG_HIBERNATE_PSL +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER +#define CONFIG_I2C_UPDATE_IF_CHANGED +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_LTO +#define CONFIG_PWM +#define CONFIG_PWM_KBLIGHT +#define CONFIG_TEMP_SENSOR +#define CONFIG_THERMISTOR_NCP15WB +#define CONFIG_VBOOT_EFS2 +#define CONFIG_VBOOT_HASH +#define CONFIG_VOLUME_BUTTONS + +/* CBI EEPROM for board version and SKU ID */ +#define CONFIG_CBI_EEPROM +#define CONFIG_BOARD_VERSION_CBI +#define CONFIG_CRC8 + +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_BATTERY_SMART +/* + * Enable support for battery hostcmd, supporting longer strings. + * + * Vilboz battery options' model names vary in the 8th character, which is + * truncated in the memory mapped battery info; differentiating them requires + * support for EC_CMD_BATTERY_GET_STATIC version 1. + */ +#define CONFIG_BATTERY_V2 +#define CONFIG_BATTERY_COUNT 1 +#define CONFIG_HOSTCMD_BATTERY_V2 + +#define CONFIG_BC12_DETECT_PI3USB9201 + +#define CONFIG_CHARGER +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER_DISCHARGE_ON_AC +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_ISL9241 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 +/* + * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging + * but that feature of ISL9241 is broken (b/160287056) so we have to use + * CONFIG_CHARGE_RAMP_SW instead. + */ +#define CONFIG_CHARGE_RAMP_SW + +#define CONFIG_CHIPSET_STONEY +#define CONFIG_CHIPSET_CAN_THROTTLE +#define CONFIG_CHIPSET_RESET_HOOK + +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM +#define CONFIG_THROTTLE_AP + +#ifdef VARIANT_ZORK_TREMBYLE + #define CONFIG_FANS FAN_CH_COUNT + #undef CONFIG_FAN_INIT_SPEED + #define CONFIG_FAN_INIT_SPEED 50 +#endif + +#define CONFIG_LED_COMMON +#define CONFIG_CMD_LEDTEST +#define CONFIG_LED_ONOFF_STATES + +/* + * On power-on, H1 releases the EC from reset but then quickly asserts and + * releases the reset a second time. This means the EC sees 2 resets: + * (1) power-on reset, (2) reset-pin reset. This config will + * allow the second reset to be treated as a power-on. + */ +#define CONFIG_BOARD_RESET_AFTER_POWER_ON + +#define CONFIG_IO_EXPANDER +#define CONFIG_IO_EXPANDER_NCT38XX + +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#undef CONFIG_KEYBOARD_VIVALDI + +/* + * USB ID + * + * This is allocated specifically for Zork + * http://google3/hardware/standards/usb/ + */ +#define CONFIG_USB_PID 0x5040 + +#define CONFIG_USB_PD_REV30 + +/* Enable the TCPMv2 PD stack */ +#define CONFIG_USB_PD_TCPMV2 + +#ifndef CONFIG_USB_PD_TCPMV2 + #define CONFIG_USB_PD_TCPMV1 +#else + #define CONFIG_USB_PD_DECODE_SOP + #define CONFIG_USB_DRP_ACC_TRYSRC + + /* Enable TCPMv2 Fast Role Swap */ + /* Turn off until FRSwap is working */ + #undef CONFIG_USB_PD_FRS_TCPC +#endif + +#define CONFIG_HOSTCMD_PD_CONTROL +#define CONFIG_CMD_TCPC_DUMP +#define CONFIG_USB_CHARGER +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_COMM_LOCKED +#define CONFIG_USB_PD_DISCHARGE_TCPC +#define CONFIG_USB_PD_DP_HPD_GPIO +#ifdef VARIANT_ZORK_TREMBYLE +/* + * Use a custom HPD function that supports HPD on IO expander. + * TODO(b/165622386) remove this when HPD is on EC GPIO. + */ +# define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM +#endif +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_USB_PD_TCPM_NCT38XX +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_PD_VBUS_DETECT_TCPC +#define CONFIG_USBC_PPC +#define CONFIG_USBC_PPC_SBU +#define CONFIG_USBC_PPC_AOZ1380 +#define CONFIG_USBC_RETIMER_PI3HDX1204 +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_SS_MUX_DFP_ONLY +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP +#define CONFIG_USB_MUX_AMD_FP5 + +#if defined(VARIANT_ZORK_TREMBYLE) + #define CONFIG_USB_PD_PORT_MAX_COUNT 2 + #define CONFIG_USBC_PPC_NX20P3483 + #define CONFIG_USBC_RETIMER_PS8802 + #define CONFIG_USBC_RETIMER_PS8818 + #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT + #define CONFIG_USB_MUX_RUNTIME_CONFIG + /* USB-A config */ + #define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L + #define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L + /* PS8818 RX Input Termination - default value */ + #define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM +#elif defined(VARIANT_ZORK_DALBOZ) + #define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT +#endif + +/* USB-A config */ +#define USB_PORT_COUNT USBA_PORT_COUNT +#define CONFIG_USB_PORT_POWER_SMART +#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY +#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP +#define CONFIG_USB_PORT_POWER_SMART_INVERTED + +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ + +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 + +/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ +#define ZORK_AC_PROCHOT_CURRENT_MA 3328 + +/* + * EC will boot AP to depthcharge if: (BAT >= 4%) || (AC >= 50W) + * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on + * Depthcharge to boot OS. + */ +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 + +/* Increase length of history buffer for port80 messages. */ +#undef CONFIG_PORT80_HISTORY_LEN +#define CONFIG_PORT80_HISTORY_LEN 256 + +/* Increase console output buffer since we have the RAM available. */ +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 4096 + +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 +#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1 +#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_EEPROM I2C_PORT_SENSOR +#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1 + +#if defined(VARIANT_ZORK_TREMBYLE) + #define CONFIG_CHARGER_RUNTIME_CONFIG + #define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 + #define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0 + #define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1 + #define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0 +#elif defined(VARIANT_ZORK_DALBOZ) + #define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0 + #define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0 + #define I2C_PORT_CHARGER NPCX_I2C_PORT2_0 +#endif + +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +#define CONFIG_MKBP_EVENT +/* Host event is required to wake from sleep */ +#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT +/* Required to enable runtime configuration */ +#define CONFIG_MKBP_EVENT_WAKEUP_MASK (BIT(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED)) + +/* Sensors */ +#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT + +/* Thermal */ +#define CONFIG_TEMP_SENSOR_SB_TSI + +#ifdef HAS_TASK_MOTIONSENSE +/* Enable sensor fifo, must also define the _SIZE and _THRES */ +#define CONFIG_ACCEL_FIFO +/* FIFO size is a power of 2. */ +#define CONFIG_ACCEL_FIFO_SIZE 256 +/* Depends on how fast the AP boots and typical ODRs. */ +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) +#endif + +/* Audio */ +#define CONFIG_AUDIO_CODEC +#define CONFIG_AUDIO_CODEC_DMIC +#define CONFIG_AUDIO_CODEC_I2S_RX + +/* CLI COMMAND */ +#define CONFIG_CMD_CHARGEN + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "math_util.h" +#include "registers.h" + +enum power_signal { + X86_SLP_S3_N, + X86_SLP_S5_N, + X86_S0_PGOOD, + X86_S5_PGOOD, + POWER_SIGNAL_COUNT +}; + +enum fan_channel { + FAN_CH_0 = 0, + /* Number of FAN channels */ + FAN_CH_COUNT, +}; + +#ifdef VARIANT_ZORK_TREMBYLE +enum usbc_port { + USBC_PORT_C0 = 0, + USBC_PORT_C1, + USBC_PORT_COUNT +}; +#endif + +enum sensor_id { + LID_ACCEL, + BASE_ACCEL, + BASE_GYRO, + SENSOR_COUNT, +}; + +/* + * Matrix to rotate accelerators into the standard reference frame. The default + * is the identity which is correct for the reference design. Variations of + * Zork may need to change it for manufacturability. + * For the lid: + * +x to the right + * +y up + * +z out of the page + * + * The principle axes of the body are aligned with the lid when the lid is in + * the 180 degree position (open, flat). + * + * Boards within the Zork family may need to modify this definition at + * board_init() time. + */ +extern mat33_fp_t zork_base_standard_ref; + +extern const struct thermistor_info thermistor_info; + +/* Sensors without hardware FIFO are in forced mode */ +#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) + +void mst_hpd_interrupt(enum ioex_signal signal); +void sbu_fault_interrupt(enum ioex_signal signal); + +#ifdef VARIANT_ZORK_TREMBYLE +void board_reset_pd_mcu(void); + +/* Common definition for the USB PD interrupt handlers. */ +void tcpc_alert_event(enum gpio_signal signal); +void bc12_interrupt(enum gpio_signal signal); +__override_proto void ppc_interrupt(enum gpio_signal signal); +#endif + +void board_print_temps(void); + +/* GPIO or IOEX signal used to set IN_HPD on DB retimer. */ +extern int board_usbc1_retimer_inhpd; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/board/atlas/board.h b/board/atlas/board.h index 5d0c042738..eda780a4fd 100644 --- a/board/atlas/board.h +++ b/board/atlas/board.h @@ -87,7 +87,6 @@ #define CONFIG_CHARGER_ISL9238 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 #define CONFIG_CHARGER_PROFILE_OVERRIDE #define CONFIG_CHARGER_PSYS #define CONFIG_CHARGER_PSYS_READ diff --git a/board/casta/board.h b/board/casta/board.h new file mode 100644 index 0000000000..934063c548 --- /dev/null +++ b/board/casta/board.h @@ -0,0 +1,95 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Casta board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Select Baseboard features */ +#define VARIANT_OCTOPUS_EC_NPCX796FB +#define VARIANT_OCTOPUS_TCPC_0_PS8751 +#define VARIANT_OCTOPUS_NO_SENSORS +#define CONFIG_CHARGER_RUNTIME_CONFIG +#include "baseboard.h" + +#define CONFIG_LED_COMMON + +/* USB PD */ +#undef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT +/* + * This board configures two chargers, one of which can measure VBUS and one of + * which cannot. Leave the default config, which defines + * CONFIG_USB_PD_VBUS_MEASURE_CHARGER. + */ + +#define CONFIG_TEMP_SENSOR +#define CONFIG_THERMISTOR + +/* + * Don't allow the system to boot to S0 when the battery is low and unable to + * communicate on locked systems (which haven't PD negotiated). + */ +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 + +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 + +/* + * Allow an additional second during power button init to let PD negotiation + * complete when we have no battery and need to meet + * CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON. SKUs which do not have a TCPC on + * port 1 will take slightly longer to complete negotiation while the PD1 task + * attempts to communicate with its TCPC before suspending. + */ +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2 + +/* Keyboard Backlight is unconnected in casta proto */ +#undef CONFIG_PWM +#undef CONFIG_PWM_KBLIGHT + +/* All casta systems are clamshells */ +#undef CONFIG_TABLET_MODE + +/* TODO(b/119872005): Casta: confirm thermistor parts */ +#define CONFIG_STEINHART_HART_3V3_13K7_47K_4050B +#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B + +/* Battery W/A */ +#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 6144 +#define CONFIG_CHARGER_PROFILE_OVERRIDE +#define CONFIG_I2C_XFER_BOARD_CALLBACK + +/* The board needs 100ms for VBUS_C[0|1]_BC12 to drop to lower VvbusUVLO */ +#undef CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS +#define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 100 + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +enum adc_channel { + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_CH_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_BATTERY, + TEMP_SENSOR_AMBIENT, + TEMP_SENSOR_CHARGER, + TEMP_SENSOR_COUNT +}; + +/* List of possible batteries */ +enum battery_type { + BATTERY_SDI, + BATTERY_TYPE_COUNT, +}; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/coral/board.h b/board/coral/board.h index a47449287c..aae0cf7b07 100644 --- a/board/coral/board.h +++ b/board/coral/board.h @@ -61,6 +61,7 @@ #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 #define CONFIG_CHARGER_MAINTAIN_VBAT +#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_USB_CHARGER #define CONFIG_CHARGER_PROFILE_OVERRIDE diff --git a/board/homestar/board.h b/board/homestar/board.h new file mode 100644 index 0000000000..1c3a114a71 --- /dev/null +++ b/board/homestar/board.h @@ -0,0 +1,126 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Homestar board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +#include "baseboard.h" + +/* On-body detection */ +#define CONFIG_BODY_DETECTION +#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL +#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */ +#define CONFIG_GESTURE_DETECTION +#define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR) +#define CONFIG_GESTURE_HOST_DETECTION + +/* TODO(waihong): Remove the following bringup features */ +#define CONFIG_BRINGUP +#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */ +#define CONFIG_USB_PD_DEBUG_LEVEL 3 +#define CONFIG_CMD_GPIO_EXTENDED +#define CONFIG_CMD_POWERINDEBUG +#define CONFIG_I2C_DEBUG +#define CONFIG_DEVICE_EVENT + +#define CONFIG_BUTTON_TRIGGERED_RECOVERY + +/* Internal SPI flash on NPCX7 */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ + +/* Switchcap */ +#define CONFIG_LN9310 + +/* Battery */ +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_VENDOR_PARAM + +/* Enable PD3.0 */ +#define CONFIG_USB_PD_REV30 + +/* BC 1.2 Charger */ +#define CONFIG_BC12_DETECT_PI3USB9201 + +/* USB */ +#define CONFIG_USB_PD_TCPM_MULTI_PS8XXX +#define CONFIG_USB_PD_TCPM_PS8755 +#define CONFIG_USB_PD_TCPM_PS8805 +#define CONFIG_USBC_PPC_SN5S330 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 + +/* BMI160 Lid accel/gyro */ +#define CONFIG_ACCELGYRO_BMI160 +#define CONFIG_ACCEL_INTERRUPTS +#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) +#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS + +#define CONFIG_TABLET_MODE +#define CONFIG_TABLET_MODE_SWITCH +#define CONFIG_GMR_TABLET_MODE +#define CONFIG_FRONT_PROXIMITY_SWITCH + +#define CONFIG_DETACHABLE_BASE +#define CONFIG_BASE_ATTACHED_SWITCH + +/* GPIO alias */ +#define GPIO_AC_PRESENT GPIO_CHG_ACOK_OD +#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL +#define GPIO_PMIC_RESIN_L GPIO_PM845_RESIN_L +/* TODO(Dolan): check which pin was used for tablet mode detect */ +#define GMR_TABLET_MODE_GPIO_L GPIO_LID_OPEN_EC +#define GPIO_SWITCHCAP_PG_INT_L GPIO_LN9310_INT + +#define CONFIG_MKBP_INPUT_DEVICES + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +enum adc_channel { + ADC_VBUS, + ADC_AMON_BMON, + ADC_PSYS, + ADC_BASE_DET, + ADC_CH_COUNT +}; + +/* Motion sensors */ +enum sensor_id { + LID_ACCEL = 0, + LID_GYRO, + SENSOR_COUNT, +}; + +enum pwm_channel { + PWM_CH_DISPLIGHT = 0, + PWM_CH_COUNT +}; + +/* List of possible batteries */ +enum battery_type { + BATTERY_GH02047XL_1C, + BATTERY_GH02047XL, + BATTERY_DS02032XL, + BATTERY_DS02032XL_1C, + BATTERY_L21D4PG0, + BATTERY_L21M4PG0, + BATTERY_TYPE_COUNT, +}; + +/* Reset all TCPCs. */ +void board_reset_pd_mcu(void); +void board_set_tcpc_power_mode(int port, int mode); +/* Base detection */ +void base_detect_interrupt(enum gpio_signal signal); + +#endif /* !defined(__ASSEMBLER__) */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h index e7dd90c54f..87961e830d 100644 --- a/board/mchpevb1/board.h +++ b/board/mchpevb1/board.h @@ -157,11 +157,6 @@ /* #define CONFIG_CHARGER_ILIM_PIN_DISABLED */ /* #define CONFIG_CHARGER_INPUT_CURRENT 512 */ -/* - * MCHP disable this for Kabylake eSPI bring up - * #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 - */ - /* #define CONFIG_CHARGER_NARROW_VDC */ /* #define CONFIG_CHARGER_PROFILE_OVERRIDE */ /* #define CONFIG_CHARGER_SENSE_RESISTOR 10 */ diff --git a/board/nami/board.h b/board/nami/board.h index 6fca31f08f..a6769e4486 100644 --- a/board/nami/board.h +++ b/board/nami/board.h @@ -96,9 +96,6 @@ #define CONFIG_CHARGER_ISL9238 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 -/* EC's thresholds. 3%: boot, 2%: no boot. Required for soft sync. */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3 -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 27000 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 /* AP's thresholds. */ diff --git a/board/nautilus/board.h b/board/nautilus/board.h index 71e253e8cd..995593ce53 100644 --- a/board/nautilus/board.h +++ b/board/nautilus/board.h @@ -79,7 +79,6 @@ #define CONFIG_CHARGER_ISL9238 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 #define CONFIG_CHARGER_PROFILE_OVERRIDE #define CONFIG_CHARGER_PSYS #define CONFIG_CHARGER_SENSE_RESISTOR 10 diff --git a/board/nocturne/board.h b/board/nocturne/board.h index 2db2a5eb79..ff1c40a456 100644 --- a/board/nocturne/board.h +++ b/board/nocturne/board.h @@ -70,6 +70,7 @@ #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 128 #define CONFIG_CHARGER_ISL9238 +#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 diff --git a/board/poppy/board.h b/board/poppy/board.h index 7337cf1363..d0f834cff5 100644 --- a/board/poppy/board.h +++ b/board/poppy/board.h @@ -87,7 +87,6 @@ #define CONFIG_CHARGER_ISL9238 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 #define CONFIG_CHARGER_PSYS #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 diff --git a/board/rammus/board.h b/board/rammus/board.h index 9b3c274eea..08e6d054ad 100644 --- a/board/rammus/board.h +++ b/board/rammus/board.h @@ -84,7 +84,6 @@ #define CONFIG_CHARGER_ISL9238 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 #define CONFIG_CHARGER_PSYS #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 diff --git a/board/reef/board.h b/board/reef/board.h index 3a148dcd45..1d541d3296 100644 --- a/board/reef/board.h +++ b/board/reef/board.h @@ -56,6 +56,7 @@ #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000 #define CONFIG_CHARGER_MAINTAIN_VBAT +#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_USB_CHARGER #define CONFIG_CHARGER_PROFILE_OVERRIDE diff --git a/board/reef_it8320/board.h b/board/reef_it8320/board.h index 85399a3cc5..09aa1300d3 100644 --- a/board/reef_it8320/board.h +++ b/board/reef_it8320/board.h @@ -46,6 +46,7 @@ #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000 #define CONFIG_CHARGER_MAINTAIN_VBAT +#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_USB_CHARGER #define CONFIG_CHARGER_PROFILE_OVERRIDE diff --git a/board/reef_mchp/board.h b/board/reef_mchp/board.h index 43fbdf4f20..21e4cfd58d 100644 --- a/board/reef_mchp/board.h +++ b/board/reef_mchp/board.h @@ -56,6 +56,7 @@ #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 18000 #define CONFIG_CHARGER_MAINTAIN_VBAT +#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_USB_CHARGER #define CONFIG_CHARGER_PROFILE_OVERRIDE diff --git a/board/samus/board.h b/board/samus/board.h index 604408c7b2..cb9d7941fe 100644 --- a/board/samus/board.h +++ b/board/samus/board.h @@ -55,6 +55,7 @@ #define CONFIG_CHARGER_INPUT_CURRENT 320 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM +#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 #define CONFIG_FANS 2 #define CONFIG_FAN_UPDATE_PERIOD 10 diff --git a/board/storo/board.h b/board/storo/board.h new file mode 100644 index 0000000000..87525dd071 --- /dev/null +++ b/board/storo/board.h @@ -0,0 +1,146 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Storo board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Select Baseboard features */ +#define VARIANT_DEDEDE_EC_IT8320 +#include "baseboard.h" + +/* EC console commands */ +#define CONFIG_CMD_TCPC_DUMP +#define CONFIG_CMD_CHARGER_DUMP + +/* Battery */ +#define CONFIG_BATTERY_FUEL_GAUGE + +/* BC 1.2 */ +#define CONFIG_BC12_DETECT_PI3USB9201 + +/* Charger */ +#define CONFIG_CHARGER_RAA489000 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC +#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) + +#define GPIO_USB_C1_INT_ODL GPIO_SUB_USB_C1_INT_ODL + +/* LED */ +#define CONFIG_LED_ONOFF_STATES +#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 + +#define I2C_PORT_ACCEL I2C_PORT_SENSOR + +/* Sensors */ +#define CONFIG_CMD_ACCELS +#define CONFIG_CMD_ACCEL_INFO + +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCELGYRO_ICM42607 + +/* Lid operates in forced mode, base in FIFO */ +#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) +#define CONFIG_ACCEL_FIFO +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) + +#define CONFIG_ACCEL_INTERRUPTS +#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) + +#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) + +#define CONFIG_LID_ANGLE +#define CONFIG_LID_ANGLE_UPDATE +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL + +#define CONFIG_TABLET_MODE +#define CONFIG_TABLET_MODE_SWITCH +#define CONFIG_GMR_TABLET_MODE + +/* TCPC */ +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_TCPM_RAA489000 + +/* USB defines specific to external TCPCs */ +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_VBUS_DETECT_TCPC +#define CONFIG_USB_PD_DISCHARGE_TCPC +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_5V_EN_CUSTOM + +/* Thermistors */ +#define CONFIG_TEMP_SENSOR +#define CONFIG_THERMISTOR +#define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B +#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_EN_PP3300_A + +/* USB Mux and Retimer */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ + +#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ + + + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +enum chg_id { + CHARGER_PRIMARY, + CHARGER_SECONDARY, + CHARGER_NUM, +}; + + + +/* Motion sensors */ +enum sensor_id { + LID_ACCEL, + BASE_ACCEL, + BASE_GYRO, + SENSOR_COUNT +}; + +/* ADC channels */ +enum adc_channel { + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_TEMP_SENSOR_3, /* ADC15*/ + ADC_CH_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_1, + TEMP_SENSOR_2, + TEMP_SENSOR_3, + TEMP_SENSOR_COUNT +}; + +/* List of possible batteries */ +enum battery_type { + BATTERY_C21N2018, + BATTERY_TYPE_COUNT, +}; + +void motion_interrupt(enum gpio_signal signal); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/common/battery.c b/common/battery.c index f048a1db91..50d689f0d1 100644 --- a/common/battery.c +++ b/common/battery.c @@ -22,7 +22,6 @@ #define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) /* See config.h for details */ -const static int batt_full_factor = CONFIG_BATT_FULL_FACTOR; const static int batt_host_full_factor = CONFIG_BATT_HOST_FULL_FACTOR; const static int batt_host_shutdown_pct = CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE; @@ -588,9 +587,6 @@ void battery_compensate_params(struct batt_params *batt) return; /* Some batteries don't update full capacity as often. */ - if (!IS_ENABLED(CONFIG_BATTERY_EXPORT_DISPLAY_SOC)) - /* full_factor is effectively disabled in powerd. */ - *full = *full * batt_full_factor / 100; if (*remain > *full) *remain = *full; @@ -625,7 +621,7 @@ void battery_compensate_params(struct batt_params *batt) batt->display_charge = 1000; } -#ifdef CONFIG_BATTERY_EXPORT_DISPLAY_SOC +#ifdef CONFIG_CHARGER static int battery_display_soc(struct host_cmd_handler_args *args) { struct ec_response_display_soc *r = args->response; diff --git a/include/config.h b/include/config.h index faa1f5ed3c..2a1e5f5759 100644 --- a/include/config.h +++ b/include/config.h @@ -492,61 +492,44 @@ #undef CONFIG_BATTERY_MEASURE_IMBALANCE /* - * If remaining capacity is x% of full capacity, remaining capacity is set - * equal to full capacity. - * * Some batteries don't update full capacity timely or don't update it at all. * On such systems, compensation is required to guarantee remaining_capacity * will be equal to full_capacity eventually. This used to be done in ACPI. * - * When CONFIG_BATTERY_EXPORT_DISPLAY_SOC is enabled, CONFIG_BATT_FULL_FACTOR - * has no effect. Also CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE is used by Powerd - * as the threshold for low battery shutdown. For example, if we have: + * Powerd uses CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE as the threshold for low + * battery shutdown. + * + * We want to show the low battery alert whenever we can. Thus, we make EC not + * inhibit power-on even if it knows the host would immediately shut down. To + * get that behavior, we need: + * + * MIN_BAT_PCT_FOR_POWER_ON < HOST_SHUTDOWN_PER = BATTERY_LEVEL_SHUTDOWN * - * CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 3 - * CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2, - * BATTERY_LEVEL_SHUTDOWN = 1 + * Thus, we set them as follows by default: * - * the battery range is divided as follows (assuming system is powered only by - * internal battery): + * CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%) + * CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2 (shutdown if soc <= 2%) + * BATTERY_LEVEL_SHUTDOWN = 3 (shutdown if soc < 3%) * - * 0% ------------------- 1% ------------------- 2% ------------------- 3% - * EC refuses to boot -> - * Powerd shuts down system -> - * EC shuts down system -> + * This produces the following behavior: + * + * - If soc = 1%, system doesn't boot. User wouldn't know why. + * - If soc = 2%, system boots. Alert is shown. System immediately shuts down. + * - If battery discharges to 2% while the system is running, system shuts down. + * If that happens while a user is away, they can press the power button to + * learn what happened. */ -#define CONFIG_BATT_FULL_FACTOR 98 -#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 +#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 2 /* shutdown if soc <= 2% */ /* * Powerd's full_factor. The value comes from: * src/platform2/power_manager/default_prefs/power_supply_full_factor * - * When CONFIG_BATTERY_EXPORT_DISPLAY_SOC is enabled, this value is exported - * to the host (i.e. Powerd). It's used to calculate the ETA for full charge. + * This value is used by the host to calculate the ETA for full charge. */ #define CONFIG_BATT_HOST_FULL_FACTOR 97 /* - * This option enables EC to be the origin of the display SoC and allows the - * host (i.e. Powerd) to retrieve it through EC_CMD_DISPLAY_SOC. - * - * The display SoC is computed from the remaining capacity, the last full - * charge, CONFIG_BATT_FULL_FACTOR, CONFIG_BATT_HOST_FULL_FACTOR, and - * CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE. - * - * If this option is disabled, the EC and the host will individually compute - * the display SoC, which may result in inconsistent behaviors since the numbers - * do not necessarily match. As such, this option is going to be enabled by - * default and the old behavior (#undef CONFIG_BATTERY_EXPORT_DISPLAY_SOC) will - * be deprecated. - * - * TODO: Define CONFIG_BATTERY_EXPORT_DISPLAY_SOC by default and remove - * CONFIG_BATTERY_EXPORT_DISPLAY_SOC and CONFIG_BATT_FULL_FACTOR. - */ -#undef CONFIG_BATTERY_EXPORT_DISPLAY_SOC - -/* * Expose some data when it is needed. * For example, battery disconnect state */ @@ -866,8 +849,8 @@ * analog signaling. If the AP requires greater than 15W to boot, then see * CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW. */ -#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON -#undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 /* Don't boot if soc < 2% */ +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1 /* Default: 15000 */ #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON /* Default: Disabled */ |