diff options
| author | Jun Lin <CHLin56@nuvoton.com> | 2022-02-16 14:15:41 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-25 07:00:38 +0000 |
| commit | 495172f0d7c8055218af9d4ffc21bda038942726 (patch) | |
| tree | 4056825cc7f447d70a8dfa41e99e07c0ffcd8af5 | |
| parent | 45d722959e18a7a865c3cf2c88d8bfc32cdf8c81 (diff) | |
| download | chrome-ec-495172f0d7c8055218af9d4ffc21bda038942726.tar.gz | |
npcx: power down unused modules
This CL sets the power down bit for unused module SDP and I3C to
get better power efficiency.
BUG=b:219388463
BRANCH=none
TEST=pass "make buiilall"
TEST=observe registers by "rw .b 0x4000d008" and "rw .b 0x4000d025"
berfore/after this CL.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Idc399af40588a650e9031c6eadffc70c058d4ac4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3467378
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
| -rw-r--r-- | chip/npcx/registers-npcx9.h | 1 | ||||
| -rw-r--r-- | chip/npcx/registers.h | 2 | ||||
| -rw-r--r-- | chip/npcx/system.c | 27 |
3 files changed, 21 insertions, 9 deletions
diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h index 1d2a02084c..2f2a22405a 100644 --- a/chip/npcx/registers-npcx9.h +++ b/chip/npcx/registers-npcx9.h @@ -327,6 +327,7 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_5 = 4, NPCX_PMC_PWDWN_6 = 5, NPCX_PMC_PWDWN_7 = 6, + NPCX_PMC_PWDWN_8 = 7, NPCX_PMC_PWDWN_CNT, }; diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index f0c241e7f9..5a140e60b8 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -616,7 +616,7 @@ enum { #define NPCX_DISIDL_CTL1 REG8(NPCX_PMC_BASE_ADDR + 0x005) #define NPCX_PWDWN_CTL_ADDR(offset) (((offset) < 6) ? \ (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \ - (NPCX_PMC_BASE_ADDR + 0x024)) + (NPCX_PMC_BASE_ADDR + 0x024 + (offset) - 6)) #define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) /* PMC register fields */ diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 1a53ee9af1..4a2450ee5f 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -33,8 +33,9 @@ /* ROM address of chip revision */ #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 -#define CHIP_REV_ADDR 0x0000FFFC -#define CHIP_REV_STR_SIZE 12 +#define CHIP_REV_ADDR 0x0000FFFC +#define CHIP_REV_STR_SIZE 12 +#define PWDWN_8_RESERVED_SET_MASK 0x30 #else #define CHIP_REV_ADDR 0x00007FFC #define CHIP_REV_STR_SIZE 6 @@ -852,15 +853,20 @@ void system_pre_init(void) * EC should be initialized in Booter */ - /* Power-down the modules we don't need */ - NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_1) = 0xF9; /* Skip SDP_PD FIU_PD */ + /* Power down KBS, SDP, PS2, UART1, and MFT1-3 */ + NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_1) = 0xFB; + /* Power down PWM0-7 */ NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_2) = 0xFF; #if defined(CHIP_FAMILY_NPCX5) - NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x0F; /* Skip GDMA */ + /* Power down SMB0-3 */ + NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x0F; #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 - NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x3F; /* Skip GDMA */ + /* Power down SMB0-4 */ + NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x3F; #endif - NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4; /* Skip ITIM2/1_PD */ + /* Power down ITIM3, ADC, PECI, SPIP */ + NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4; + /* Power down C2HACC, SHM_REG, SHM, Port80, and MSWC */ NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8; pwdwn6 = 0x70 | @@ -871,7 +877,7 @@ void system_pre_init(void) */ BIT(NPCX_PWDWN_CTL6_ITIM6_PD) | #endif - BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */ + BIT(NPCX_PWDWN_CTL6_ITIM4_PD); #if !defined(CONFIG_HOST_INTERFACE_ESPI) pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD; #endif @@ -881,13 +887,18 @@ void system_pre_init(void) #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ defined(CHIP_VARIANT_NPCX7M7WC) + /* Power down UART2, SMB5-7, ITIM64, and WoV */ NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7; #else + /* Power down SMB5-7 */ NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07; #endif #endif #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + /* Power down UART2-4, SMB5-7, and ITIM64 */ NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xFF; + /* Power down I3C */ + NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_8) = PWDWN_8_RESERVED_SET_MASK | 0x01; #endif /* Following modules can be powered down automatically in npcx7 */ |