diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2023-04-19 14:15:34 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-05-05 03:03:31 +0000 |
| commit | 1ab28435709772a9b6fe1bd6a7bad0b9e3da8ff4 (patch) | |
| tree | 31522b8f9b90bcf205ff1def71905f18737fbba3 | |
| parent | aeeadc2b31fa829b66c1e4366346d2dc81d03e76 (diff) | |
| download | chrome-ec-1ab28435709772a9b6fe1bd6a7bad0b9e3da8ff4.tar.gz | |
Hades: Configure GPIOs (2)
This CL configures GPIO pins according to the latest schematics.
This includes the following changes:
* GPIOC4, GPIOC3, GPIOC2, GPIO60: OUT_LOW -> OUT_HIGH
* GPIO62: INT_FALLING -> GPIO_OUT_LOW
* GPIOD2: Add GPIO_PULL_UP
* GPIOD4: ODR_LOW -> OUT_HIGH
BUG=b:272815831
TEST=make BOARD=hades
Change-Id: I0ef7b5984a0e9b21c838b97f5059b9ddb4dd879f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4507758
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Commit-Queue: Tarun Tuli <taruntuli@google.com>
Tested-by: Tarun Tuli <taruntuli@google.com>
| -rw-r--r-- | board/hades/gpio.inc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/hades/gpio.inc b/board/hades/gpio.inc index 86da520097..318a14906c 100644 --- a/board/hades/gpio.inc +++ b/board/hades/gpio.inc @@ -12,7 +12,7 @@ GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAK GPIO_INT(EC_PROCHOT_IN_L, PIN(A, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt) GPIO_INT(EC_WP_ODL, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) GPIO_INT(GSC_EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt) -GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_PULL_UP | GPIO_HIB_WAKE_HIGH, lid_interrupt) GPIO_INT(SEQ_EC_ALL_SYS_PG, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SEQ_EC_DSW_PWROK, PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SEQ_EC_RSMRST_ODL, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) @@ -22,7 +22,6 @@ GPIO_INT(SYS_SLP_S0IX_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_ GPIO_INT(USB_C0_BC12_INT_ODL, PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(USB_C0_TCPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(USB_C0_PPC_INT_ODL, PIN(A, 7), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(USB_C0_IN_HPD, PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt) GPIO_INT(USB_C1_BC12_INT_ODL, PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(USB_C1_TCPC_INT_ODL, PIN(7, 0), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(USB_C1_PPC_INT_ODL, PIN(B, 1), GPIO_INT_FALLING, ppc_interrupt) @@ -66,14 +65,15 @@ GPIO(EC_USB_PCH_C1_OC_ODL, PIN(9, 7), GPIO_ODR_HIGH) GPIO(VCCST_PWRGD_OD, PIN(A, 4), GPIO_ODR_LOW) GPIO(EN_USB_A_LOW_POWER, PIN(9, 3), GPIO_OUT_LOW) GPIO(EN_USB_C1_28V, PIN(B, 5), GPIO_OUT_LOW) -GPIO(USB_C0_TCPC_RST_ODL, PIN(D, 4), GPIO_ODR_LOW) +GPIO(USB_C0_TCPC_RST_ODL, PIN(D, 4), GPIO_OUT_HIGH) GPIO(NVIDIA_GPU_ACOFF_ODL, PIN(5, 6), GPIO_ODR_HIGH) -GPIO(LED_4_L, PIN(6, 0), GPIO_OUT_LOW) -GPIO(LED_3_L, PIN(C, 2), GPIO_OUT_LOW) -GPIO(LED_2_L, PIN(C, 3), GPIO_OUT_LOW) -GPIO(LED_1_L, PIN(C, 4), GPIO_OUT_LOW) +GPIO(LED_4_L, PIN(6, 0), GPIO_OUT_HIGH) +GPIO(LED_3_L, PIN(C, 2), GPIO_OUT_HIGH) +GPIO(LED_2_L, PIN(C, 3), GPIO_OUT_HIGH) +GPIO(LED_1_L, PIN(C, 4), GPIO_OUT_HIGH) GPIO(USB_C0_PPC_HI_ILIM, PIN(F, 2), GPIO_OUT_HIGH) GPIO(USB_C1_PPC_HI_ILIM, PIN(F, 3), GPIO_OUT_HIGH) +GPIO(USB_C0_IN_HPD, PIN(6, 2), GPIO_OUT_LOW) /* Block AP power sequencing (b/279214842) */ GPIO(PG_PP3300_S5_OD, PIN(B, 4), GPIO_ODR_HIGH) |