diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2018-04-26 09:48:09 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2018-08-28 21:19:18 +0000 |
| commit | 93d992e8fa82a0f177a8f6564025adb02855e529 (patch) | |
| tree | d65ca65cc71551c1d162ce674aa9cc509420fde4 | |
| parent | 82185d64ee6d4115f19a5eee700b187ddf4eebfe (diff) | |
| download | chrome-ec-93d992e8fa82a0f177a8f6564025adb02855e529.tar.gz | |
Fizz: Configure USB_C0_PD_RST_ODL as GPIO_ODR_HIGH
USB_C0_PD_RST_ODL is connected to PS8751 reset pin and currently configured
as GPIO_OUT_LOW. This causes the EC to generate an unintentional reset
pulse when Cr50 resets the EC on power-on reset. When PS8751 is in reset,
the CC line is pulled low. This unintentional reset lasts longer than
tPDDebounce ("CC Timing" in the USB Type-C spec), thus causes Z32 to bring
down VBUS and the system to brown out.
This patch configures the pin as GPIO_ODR_HIGH. This will remove the
unintended reset pulse. This pin will continue to be used to generate a
reset pulse as it has been doing without exceeding tPDDebounce.
BUG=b:74354232
BRANCH=none
TEST=Verify Fizz boots on HP Z32 by:
1. Cold reboot (by servo) and
2. Plug-in USB-C cable (connected to Z32)
Change-Id: Ieae7c25e8261cf3b708e76c8340b07af5a61720f
Reviewed-on: https://chromium-review.googlesource.com/1031736
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | board/fizz/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/fizz/gpio.inc b/board/fizz/gpio.inc index 75c7130bf5..1c24925e6c 100644 --- a/board/fizz/gpio.inc +++ b/board/fizz/gpio.inc @@ -73,7 +73,7 @@ GPIO(I2C3_SDA, PIN(D, 0), GPIO_INPUT) /* EC_THEM_SDA */ GPIO(USB_C0_5V_EN, PIN(4, 2), GPIO_OUT_LOW | GPIO_PULL_UP) /* C0 5V Enable */ GPIO(USB_C0_CHARGE_L, PIN(C, 0), GPIO_OUT_LOW) /* C0 Charge enable */ GPIO(AC_JACK_CHARGE_L, PIN(C, 3), GPIO_OUT_LOW) /* AC jack charge enable */ -GPIO(USB_C0_PD_RST_ODL, PIN(0, 3), GPIO_OUT_LOW) /* C0 PD Reset */ +GPIO(USB_C0_PD_RST_ODL, PIN(0, 3), GPIO_ODR_HIGH) /* C0 PD Reset */ GPIO(USB_C0_DP_HPD, PIN(9, 4), GPIO_INPUT) /* C0 DP Hotplug Detect */ GPIO(USB_C0_TCPC_PWR, PIN(8, 4), GPIO_OUT_LOW) /* Enable C0 TCPC Power */ GPIO(FAN_PWR_EN, PIN(9, 5), GPIO_OUT_HIGH) /* Fan power */ |