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| author | Jett Rink <jettrink@chromium.org> | 2018-02-14 16:02:23 -0700 |
|---|---|---|
| committer | Daisuke Nojiri <dnojiri@chromium.org> | 2018-02-19 10:33:13 -0800 |
| commit | ecff599948fba01df364a0cf0d0078d0604c2852 (patch) | |
| tree | 4d2bd3a4de8bc0d158386d055c41df67f6bb9124 | |
| parent | 2283decc892711e9e4060f32b6de4864bbbb6f94 (diff) | |
| download | chrome-ec-ecff599948fba01df364a0cf0d0078d0604c2852.tar.gz | |
lpc: Removing unnecessary register writes
According to Nuvoton datasheet, when SHM windows are in IO mode, only the
bottom 16-bits of registers @ offset xF4 and xF8 are used.
"This register is ignored when WRAM1_IO bit in WIN_CFG register is set to
1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This
register is set to its default value by Host Domain reset."
BRANCH=none
BUG=none
TEST=boot grunt and verify host communication still works.
Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919006
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
| -rw-r--r-- | chip/npcx/lpc.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index fa3f8c8a29..57d147ed4c 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -765,14 +765,9 @@ void host_register_init(void) /* WIN1&2 mapping to IO */ lpc_sib_write_reg(SIO_OFFSET, 0xF1, lpc_sib_read_reg(SIO_OFFSET, 0xF1) | 0x30); - /* Host Command on the IO:0x0800 */ - lpc_sib_write_reg(SIO_OFFSET, 0xF7, 0x00); - lpc_sib_write_reg(SIO_OFFSET, 0xF6, 0x00); + /* WIN1 as Host Command on the IO:0x0800 */ lpc_sib_write_reg(SIO_OFFSET, 0xF5, 0x08); lpc_sib_write_reg(SIO_OFFSET, 0xF4, 0x00); - /* WIN1 as Host Command on the IO:0x0800 */ - lpc_sib_write_reg(SIO_OFFSET, 0xFB, 0x00); - lpc_sib_write_reg(SIO_OFFSET, 0xFA, 0x00); /* WIN2 as MEMMAP on the IO:0x900 */ lpc_sib_write_reg(SIO_OFFSET, 0xF9, 0x09); lpc_sib_write_reg(SIO_OFFSET, 0xF8, 0x00); |