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authorTommy Chung <tommy.chung@quanta.corp-partner.google.com>2022-07-29 11:28:01 +0800
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>2022-10-21 12:04:06 +0000
commit870b27e07c32ceddeb7b20242cae6f8fb27076ae (patch)
tree284f471ecf9cd5f7da8ce3dc83108aa5d37f5532
parente92e95683eb8bb0f8ea0d9b4601b295876198574 (diff)
downloadchrome-ec-870b27e07c32ceddeb7b20242cae6f8fb27076ae.tar.gz
dojo: Add suspend_resume_power_signal_interrupt
Put nvme_enable in AP_IN_SLEEP_L interrput routine to ensure that the timing of EN_PP3300_SSD can be enabled right after chipset resume so that the PCIe driver timeout will not happen. BUG=b:236790585 BRANCH=cherry TEST=make sure nvme enable timing will not cause PCIe driver timeout when chipset resume. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I34e1c6ad820cb33cdba272dc6f1f22fd52eeacc7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3793403 Reviewed-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Devin Lu <devin.lu@quantatw.com> (cherry picked from commit 4c145878ab754468cdb67fa10543063f902f47fe) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3967914 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
-rw-r--r--board/dojo/board.c37
-rw-r--r--board/dojo/board.h7
-rw-r--r--board/dojo/gpio.inc3
3 files changed, 34 insertions, 13 deletions
diff --git a/board/dojo/board.c b/board/dojo/board.c
index 2e11535ca3..2cf017ce37 100644
--- a/board/dojo/board.c
+++ b/board/dojo/board.c
@@ -24,6 +24,7 @@
#include "hooks.h"
#include "keyboard_scan.h"
#include "motion_sense.h"
+#include "power.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "system.h"
@@ -470,6 +471,24 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
}
+/* NVME */
+static void nvme_enable(int enable)
+{
+ gpio_set_level(GPIO_EN_PP3300_SSD, enable);
+}
+
+void suspend_resume_power_signal_interrupt(enum gpio_signal signal)
+{
+ /* AP resume */
+ if (gpio_get_level(signal) == GPIO_SIGNAL_RESUME)
+ nvme_enable(1);
+ /* AP suspend */
+ else
+ nvme_enable(0);
+
+ power_signal_interrupt(signal);
+}
+
/* Initialize board. */
static void board_init(void)
{
@@ -483,23 +502,17 @@ static void board_init(void)
/* Store base sensor to recognize which base sensor we are using */
base_sensor = get_cbi_ssfc_base_sensor();
+ /* Make sure that nvme can be enabled/disabled when board init */
+ if (gpio_get_level(GPIO_AP_IN_SLEEP_L) == GPIO_SIGNAL_RESUME)
+ nvme_enable(1);
+ else
+ nvme_enable(0);
+
board_update_motion_sensor_config();
board_update_vol_up_key();
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-static void enable_nvme(void)
-{
- gpio_set_level(GPIO_EN_PP3300_SSD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, enable_nvme, HOOK_PRIO_FIRST);
-
-static void disable_nvme(void)
-{
- gpio_set_level(GPIO_EN_PP3300_SSD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, disable_nvme, HOOK_PRIO_DEFAULT);
-
static void board_do_chipset_resume(void)
{
gpio_set_level(GPIO_EN_KB_BL, 1);
diff --git a/board/dojo/board.h b/board/dojo/board.h
index 6ce2f3ba47..fc66c84e0d 100644
--- a/board/dojo/board.h
+++ b/board/dojo/board.h
@@ -155,6 +155,13 @@ struct vol_up_key {
uint8_t col;
};
+/* AP in sleep power signal */
+enum ap_in_sleep_l_signal {
+ GPIO_SIGNAL_SUSPEND = 0,
+ GPIO_SIGNAL_RESUME,
+};
+void suspend_resume_power_signal_interrupt(enum gpio_signal signal);
+
int board_accel_force_mode_mask(void);
void motion_interrupt(enum gpio_signal signal);
diff --git a/board/dojo/gpio.inc b/board/dojo/gpio.inc
index 01cf57258d..6ec5c9c5db 100644
--- a/board/dojo/gpio.inc
+++ b/board/dojo/gpio.inc
@@ -24,7 +24,8 @@ GPIO_INT(AP_EC_WARM_RST_REQ, PIN(D, 3), GPIO_INT_RISING | GPIO_SEL_1P8V,
GPIO_INT(AP_EC_WATCHDOG_L, PIN(C, 7), GPIO_INT_BOTH | GPIO_SEL_1P8V,
chipset_watchdog_interrupt)
GPIO_INT(AP_IN_SLEEP_L, PIN(F, 2),
- GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)
+ GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V,
+ suspend_resume_power_signal_interrupt)
GPIO_INT(PMIC_EC_PWRGD, PIN(F, 3),
GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, power_signal_interrupt)