diff options
| author | Divya Jyothi <divya.jyothi@intel.com> | 2015-05-04 22:10:04 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-05 21:42:20 +0000 |
| commit | 3664b8229473bfbbb08fd61b3dacd1c9a630b5c6 (patch) | |
| tree | 240fec3eeee9a3d5aa6b39dc3d3e748631f32ae1 | |
| parent | ddf83269b46379370ff60f4fccc89ce5457fe89b (diff) | |
| download | chrome-ec-3664b8229473bfbbb08fd61b3dacd1c9a630b5c6.tar.gz | |
mec1322:Flasherase, flashread, flashwrite offsets adjusted.
Flash read,erase and write should access SPI flash
and not read SRAM MAPPED location.
flashrom -p and Software sync use the same flash functions to
perform flashread,flashearse and flashwrite.So these functions
should be reading RW image starting address offset.Address offset
sent by host should not depend on the actual SPI flash as the EC
code handles the right offset to program the ec.bin(via flashrom -p)
and RW image only via software sync.
BUG=chrome-os-partner:38103
BRANCH=None
TEST=flashrom -p options tested to read and update ec.bin
Change-Id: I3fb16accf3e05eaa3469a8a589962164574d5fb2
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/269231
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/mec1322/config_chip.h | 4 | ||||
| -rw-r--r-- | chip/mec1322/flash.c | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index 8129ee469c..3accdfdf63 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -144,8 +144,8 @@ which contains Loader and RO Images */ /* Non-memmapped, external SPI */ -/* #define CONFIG_CODERAM_ARCH -#undef CONFIG_FLASH_MAPPED*/ +/* #define CONFIG_CODERAM_ARCH*/ +#undef CONFIG_FLASH_MAPPED #undef CONFIG_FLASH_PSTATE #define CONFIG_SPI_FLASH diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c index fb6f56fc48..e9c752e917 100644 --- a/chip/mec1322/flash.c +++ b/chip/mec1322/flash.c @@ -27,6 +27,8 @@ int flash_physical_read(int offset, int size, char *data) { int ret; + offset += CONFIG_FLASH_BASE_SPI; + /* Fail if offset, size, and data aren't at least word-aligned */ if ((offset | size | (uint32_t)(uintptr_t)data) & 3) return EC_ERROR_INVAL; @@ -50,6 +52,8 @@ int flash_physical_write(int offset, int size, const char *data) { int ret, i, write_size; + offset += CONFIG_FLASH_BASE_SPI; + /* Fail if offset, size, and data aren't at least word-aligned */ if ((offset | size | (uint32_t)(uintptr_t)data) & 3) return EC_ERROR_INVAL; @@ -81,6 +85,7 @@ int flash_physical_erase(int offset, int size) { int ret; + offset += CONFIG_FLASH_BASE_SPI; spi_enable(1); ret = spi_flash_erase(offset, size); spi_enable(0); |