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authorDominic Chen <ddchen@chromium.org>2014-06-02 14:07:34 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-06-03 02:25:34 +0000
commite6755ca4ac9e92e1b1c5bab4336034a06b809926 (patch)
treed3349c84abefa2038f8e87ed14dafb365aa38d18
parenta6bf597bbc687fb0a1bc1886cb49195743342a3e (diff)
downloadchrome-ec-e6755ca4ac9e92e1b1c5bab4336034a06b809926.tar.gz
stm32: add SPI register definitions and refactor
refactor existing code in usb_pd_phy.c to use new register definitions BRANCH=none BUG=none TEST=manually verify macro substitutions produce same value Change-Id: Ia0cd815164b0262640425abd6da973c170163f2f Signed-off-by: Dominic Chen <ddchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202392 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
-rw-r--r--chip/stm32/registers.h6
-rw-r--r--chip/stm32/usb_pd_phy.c6
2 files changed, 8 insertions, 4 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 3741a38c69..c3e0f19e49 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -688,9 +688,11 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
#define STM32_SPI_CR1_MSTR (1 << 2)
#define STM32_SPI_CR1_CPOL (1 << 1)
#define STM32_SPI_CR1_CPHA (1 << 0)
+#define STM32_SPI_CR2_FRXTH (1 << 12)
+#define STM32_SPI_CR2_NSSP (1 << 3)
#define STM32_SPI_CR2_RXNEIE (1 << 6)
-#define STM32_SPI_CR2_SSOE (1 << 2)
#define STM32_SPI_CR2_RXDMAEN (1 << 0)
+#define STM32_SPI_CR2_SSOE (1 << 2)
#define STM32_SPI_CR2_TXDMAEN (1 << 1)
#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8)
@@ -698,6 +700,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
#define STM32_SPI_SR_TXE (1 << 1)
#define STM32_SPI_SR_CRCERR (1 << 4)
#define STM32_SPI_SR_BSY (1 << 7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
/* --- Debug --- */
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
index 39f898d84c..44888163c1 100644
--- a/chip/stm32/usb_pd_phy.c
+++ b/chip/stm32/usb_pd_phy.c
@@ -291,14 +291,14 @@ void pd_tx_done(int polarity)
dma_wait(DMAC_SPI_TX);
/* wait for real end of transmission */
#ifdef CHIP_FAMILY_STM32F0
- while ((spi->sr & (3<<11)))
+ while (spi->sr & STM32_SPI_SR_FTLVL)
; /* wait for TX FIFO empty */
#else
- while (!(spi->sr & (1<<1)))
+ while (!(spi->sr & STM32_SPI_SR_TXE))
; /* wait for TXE == 1 */
#endif
- while (spi->sr & (1<<7))
+ while (spi->sr & STM32_SPI_SR_BSY)
; /* wait for BSY == 0 */
/*