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author | Randall Spangler <rspangler@chromium.org> | 2014-02-06 13:14:16 -0800 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-02-07 04:15:43 +0000 |
commit | 36d4ecb153518623945f0a8e89e4413938d38869 (patch) | |
tree | d8cf2f429c4def212ffc9481e4e8e66091636056 | |
parent | 6ff7a74006d5b4ee74091e196d81c17bb8bb0578 (diff) | |
download | chrome-ec-36d4ecb153518623945f0a8e89e4413938d38869.tar.gz |
lm4: Remove 500k clock delay in clock_init()
We copied that delay because it seemed to be necessary on early LM4
chips to avoid glitching the UART. But on current boards (e.g. rambi)
this does not seem to be necessary, and delays boot by 31ms. So,
remove the delay.
BUG=chrome-os-partner:23794
BRANCH=rambi
TEST=boot system; see little to no glitching on EC uart, and system boots ok
hibernate 1; see little to no glitching on EC uart, and system boots ok
Change-Id: I9d4b5927da4282e47e1b09be838104c64f25268c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185232
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
-rw-r--r-- | chip/lm4/clock.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/chip/lm4/clock.c b/chip/lm4/clock.c index 4fa72c5ca1..04b86fae92 100644 --- a/chip/lm4/clock.c +++ b/chip/lm4/clock.c @@ -167,16 +167,6 @@ void clock_init(void) LM4_SYSTEM_MOSCCTL = 0x04; #endif - /* - * TODO(crosbug.com/p/23794): UART seems to glitch unless we wait 500k - * cycles before enabling the PLL, but only if this is a cold boot. - * Why? UART doesn't even use the PLL'd system clock. I've heard - * rumors the Stellaris ROM library does this too, but why? Revisit on - * current systems to see if this is is still needed. - */ - if (!system_jumped_to_this_image()) - clock_wait_cycles(500000); - /* Make sure PLL is disabled */ disable_pll(); } |