cortex-m/m0: Add Debug Halting Control and Status Register

For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register,
DHCSR" in the ARMv6-M Architecture Reference Manual.

For other Cortex-M, see "C1.6.2 Debug Halting Control and Status
Register, DHCSR" in the ARMv7-M Architecture Reference Manual or
https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register.

BRANCH=none
BUG=b:180144572
TEST=Using Segger J-Trace Pro with icetower v0.1, verify
     debugger_is_connected is true when debugger is attached and false
     otherwise

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I748fc26c0db4351be5a83086fdb843e5651b5425
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2713753
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>

6 files changed, 53 insertions, 2 deletions

diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
index 2bcf32317d..ad7ab6eacc 100644
--- a/core/cortex-m/build.mk
+++ b/core/cortex-m/build.mk
@@ -24,7 +24,7 @@ CFLAGS_CPU+=-flto
 LDFLAGS_EXTRA+=-flto
 endif
 
-core-y=cpu.o init.o ldivmod.o llsr.o uldivmod.o vecttable.o
+core-y=cpu.o debug.o init.o ldivmod.o llsr.o uldivmod.o vecttable.o
 core-$(CONFIG_AES)+=aes.o
 core-$(CONFIG_AES_GCM)+=ghash.o
 core-$(CONFIG_ARMV7M_CACHE)+=cache.o
diff --git a/core/cortex-m/debug.c b/core/cortex-m/debug.c
new file mode 100644
index 0000000000..db8891b5d8
--- /dev/null
+++ b/core/cortex-m/debug.c
@@ -0,0 +1,12 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "debug.h"
+#include "stdbool.h"
+
+bool debugger_is_connected(void)
+{
+	return CPU_DHCSR & DHCSR_C_DEBUGEN;
+}
diff --git a/core/cortex-m/debug.h b/core/cortex-m/debug.h
new file mode 100644
index 0000000000..ae5ef08d06
--- /dev/null
+++ b/core/cortex-m/debug.h
@@ -0,0 +1,37 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_DEBUG_H
+#define __CROS_EC_DEBUG_H
+
+#include "common.h"
+#include "stdbool.h"
+
+/* For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR"
+ * in the ARMv6-M Architecture Reference Manual.
+ *
+ * For other Cortex-M, see
+ * "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M
+ * Architecture Reference Manual or
+ * https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register.
+ */
+#define CPU_DHCSR REG32(0xE000EDF0)
+#define DHCSR_C_DEBUGEN BIT(0)
+#define DHCSR_C_HALT BIT(1)
+#define DHCSR_C_STEP BIT(2)
+#define DHCSR_C_MASKINTS BIT(3)
+#ifndef CHIP_CORE_CORTEX_M0
+#define DHCSR_C_SNAPSTALL BIT(5) /* Not available on Cortex-M0 */
+#endif
+#define DHCSR_S_REGRDY BIT(16)
+#define DHCSR_S_HALT BIT(17)
+#define DHCSR_S_SLEEP BIT(18)
+#define DHCSR_S_LOCKUP BIT(19)
+#define DHCSR_S_RETIRE_ST BIT(24)
+#define DHCSR_S_RESET_ST BIT(25)
+
+bool debugger_is_connected(void);
+
+#endif /* __CROS_EC_DEBUG_H */
diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk
index a314976bce..b0136f347e 100644
--- a/core/cortex-m0/build.mk
+++ b/core/cortex-m0/build.mk
@@ -20,7 +20,7 @@ CFLAGS_CPU+=-flto
 LDFLAGS_EXTRA+=-flto
 endif
 
-core-y=cpu.o init.o thumb_case.o div.o lmul.o ldivmod.o mula.o uldivmod.o
+core-y=cpu.o debug.o init.o thumb_case.o div.o lmul.o ldivmod.o mula.o uldivmod.o
 core-y+=vecttable.o __builtin.o
 core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o
 core-$(CONFIG_COMMON_RUNTIME)+=switch.o task.o
diff --git a/core/cortex-m0/debug.c b/core/cortex-m0/debug.c
new file mode 120000
index 0000000000..3cada87897
--- /dev/null
+++ b/core/cortex-m0/debug.c
@@ -0,0 +1 @@
+../cortex-m/debug.c
\ No newline at end of file
diff --git a/core/cortex-m0/debug.h b/core/cortex-m0/debug.h
new file mode 120000
index 0000000000..d79be16190
--- /dev/null
+++ b/core/cortex-m0/debug.h
@@ -0,0 +1 @@
+../cortex-m/debug.h
\ No newline at end of file