diff options
| author | Peter Marheine <pmarheine@chromium.org> | 2019-11-11 11:01:30 +1100 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-18 05:46:22 +0000 |
| commit | 55d2b5df418421db5fcffae3d4c2af847feafe0c (patch) | |
| tree | ae29eea66a2621e064865dee58e4bc0f9ddcfe5f | |
| parent | 46e72f0f0bbd64ebbf761a32c026e742e8c82e60 (diff) | |
| download | chrome-ec-55d2b5df418421db5fcffae3d4c2af847feafe0c.tar.gz | |
puff: use cometlake-discrete power driver
BUG=b:143188569
TEST=make buildall still succeeds
BRANCH=none
Change-Id: I9193878c65b20293fad5914af88ea4e49be369a8
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1913939
Reviewed-by: Andrew McRae <amcrae@chromium.org>
| -rw-r--r-- | board/puff/board.h | 4 | ||||
| -rw-r--r-- | board/puff/gpio.inc | 29 |
2 files changed, 15 insertions, 18 deletions
diff --git a/board/puff/board.h b/board/puff/board.h index 374ed9aebe..81fe94f363 100644 --- a/board/puff/board.h +++ b/board/puff/board.h @@ -63,7 +63,7 @@ #define CONFIG_CMD_PPC_DUMP /* Chipset config */ -#define CONFIG_CHIPSET_COMETLAKE +#define CONFIG_CHIPSET_COMETLAKE_DISCRETE /* check */ #define CONFIG_CHIPSET_CAN_THROTTLE #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK @@ -155,7 +155,7 @@ #define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 #define I2C_ADDR_EEPROM_FLAGS 0x50 -#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD) +#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD) #define CEC_GPIO_OUT GPIO_CEC_OUT #define CEC_GPIO_IN GPIO_CEC_IN diff --git a/board/puff/gpio.inc b/board/puff/gpio.inc index ceed47ece4..f578c2b6c9 100644 --- a/board/puff/gpio.inc +++ b/board/puff/gpio.inc @@ -14,13 +14,22 @@ GPIO_INT(EC_WP_ODL, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) GPIO_INT(H1_EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) /* Power sequencing interrupts */ -GPIO_INT(SLP_S0_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) -#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt) -#endif +GPIO_INT(PG_PP5000_A_OD, PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_PP1800_A_OD, PIN(3, 1), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_VPRIM_CORE_A_OD, PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_PP1050_A_OD, PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt) #ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 GPIO_INT(SLP_S4_L, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt) #endif +GPIO_INT(PG_PP2500_DRAM_U_OD, PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PG_PP1200_U_OD, PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt) +#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 +GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt) +#endif +GPIO_INT(PG_PP950_VCCIO_OD, PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SLP_S0_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(CPU_C10_GATE_L, PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(IMVP8_VRRDY_OD, PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Other interrupts */ GPIO_INT(USB_C0_TCPPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, ppc_interrupt) @@ -35,19 +44,8 @@ GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_ODR_HIGH) GPIO(EC_PCH_WAKE_ODL, PIN(7, 4), GPIO_ODR_HIGH) GPIO(EC_PROCHOT_IN_OD, PIN(3, 4), GPIO_INPUT) GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) -GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH) -/* Power inputs - these may need to be interrupts */ -GPIO(PG_VPRIM_CORE_A_OD, PIN(2, 3), GPIO_INPUT) -GPIO(IMVP8_VRRDY_OD, PIN(1, 6), GPIO_INPUT) -GPIO(PG_PP5000_A_OD, PIN(D, 7), GPIO_INPUT) -GPIO(PG_PP2500_DRAM_U_OD, PIN(2, 0), GPIO_INPUT) -GPIO(PG_PP1800_A_OD, PIN(3, 1), GPIO_INPUT) -GPIO(PG_PP1200_U_OD, PIN(2, 1), GPIO_INPUT) -GPIO(PG_PP1050_A_OD, PIN(2, 2), GPIO_INPUT) -GPIO(PG_PP950_VCCIO_OD, PIN(1, 7), GPIO_INPUT) - /* Power control outputs */ GPIO(EN_PP5000_A, PIN(A, 4), GPIO_OUT_LOW) GPIO(EN_PP3300_INA_H1_EC_ODL, PIN(5, 7), GPIO_ODR_HIGH) @@ -56,7 +54,6 @@ GPIO(VCCST_PG_OD, PIN(1, 4), GPIO_ODR_HIGH) GPIO(EN_S0_RAILS, PIN(1, 1), GPIO_OUT_LOW) GPIO(EN_ROA_RAILS, PIN(A, 3), GPIO_OUT_LOW) GPIO(EN_PP950_VCCIO, PIN(1, 0), GPIO_OUT_LOW) - GPIO(EC_IMVP8_PE, PIN(A, 7), GPIO_OUT_LOW) GPIO(EN_IMVP8_VR, PIN(F, 4), GPIO_OUT_LOW) |