diff options
| author | Keith Short <keithshort@chromium.org> | 2019-11-13 13:20:49 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-11-15 06:16:39 +0000 |
| commit | 188b6ff7d7b4e4139c16df188728f47ae81a4e00 (patch) | |
| tree | 3571d3bc0be47152ebb12921d9f73a06827f46ba | |
| parent | bb17ab2f5012784d94fb6564fbbd2c84b14f2586 (diff) | |
| download | chrome-ec-188b6ff7d7b4e4139c16df188728f47ae81a4e00.tar.gz | |
icelake/tigerlake: add option to enable PP3300 before PP5000
On Volteer, to avoid leakage from PP3300_A rail to PP5000 rail, turn on
the PP3300 rail before PP5000.
BUG=none
BRANCH=none
TEST=make buildall -j
TEST=verify Volteer transitions to S0
Change-Id: Ic86f97dbdde6d6c904fe7efc8b0edc1ead727cf6
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918603
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
| -rw-r--r-- | baseboard/volteer/baseboard.h | 1 | ||||
| -rw-r--r-- | include/config.h | 7 | ||||
| -rw-r--r-- | power/icelake.c | 31 |
3 files changed, 28 insertions, 11 deletions
diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h index 90a8c646a4..4d3936b6cd 100644 --- a/baseboard/volteer/baseboard.h +++ b/baseboard/volteer/baseboard.h @@ -32,6 +32,7 @@ /* Chipset config */ #define CONFIG_CHIPSET_TIGERLAKE +#define CONFIG_CHIPSET_PP3300_RAIL_FIRST #define CONFIG_CHIPSET_X86_RSMRST_DELAY #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_CPU_PROCHOT_ACTIVE_LOW diff --git a/include/config.h b/include/config.h index e92a20f411..921eb0f4c9 100644 --- a/include/config.h +++ b/include/config.h @@ -1106,6 +1106,13 @@ #undef CONFIG_CHIPSET_RESET_HOOK /* + * Enable turning on PP3300_A rail before PP5000_A rail on the Ice Lake + * and Tiger Lake chipsets. Enable this option if there is leakage from PP5000_A + * resources into PP3300_A resources. + */ +#undef CONFIG_CHIPSET_PP3300_RAIL_FIRST + +/* * Enable if chipset requires delay between power signals going high * and deasserting RSMRST to PCH. */ diff --git a/power/icelake.c b/power/icelake.c index f67787a5ac..99981e32a4 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -88,11 +88,10 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) GPIO_SET_LEVEL(GPIO_EN_PP3300_A, 0); /* Turn off PP5000 rail */ -#ifdef CONFIG_POWER_PP5000_CONTROL - power_5v_enable(task_get_current(), 0); -#else - GPIO_SET_LEVEL(GPIO_EN_PP5000, 0); -#endif + if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL)) + power_5v_enable(task_get_current(), 0); + else + GPIO_SET_LEVEL(GPIO_EN_PP5000, 0); /* * TODO(b/111810925): Replace this wait with @@ -141,6 +140,15 @@ __overridable void board_icl_tgl_all_sys_pwrgood(void) } +static void enable_pp5000_rail(void) +{ + if (IS_ENABLED(CONFIG_POWER_PP5000_CONTROL)) + power_5v_enable(task_get_current(), 1); + else + GPIO_SET_LEVEL(GPIO_EN_PP5000, 1); + +} + enum power_state power_handle_state(enum power_state state) { int dswpwrok_in = gpio_get_level(GPIO_PG_EC_DSW_PWROK); @@ -165,12 +173,9 @@ enum power_state power_handle_state(enum power_state state) switch (state) { case POWER_G3S5: - /* Turn on PP5000 rail */ -#ifdef CONFIG_POWER_PP5000_CONTROL - power_5v_enable(task_get_current(), 1); -#else - gpio_set_level(GPIO_EN_PP5000, 1); -#endif + /* Default behavior - turn on PP5000 rail first */ + if (!IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST)) + enable_pp5000_rail(); /* * TODO(b/111121615): Should modify this to wait until the @@ -194,6 +199,10 @@ enum power_state power_handle_state(enum power_state state) CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in); dswpwrok_out = dswpwrok_in; + /* Turn on PP5000 after PP3300 and DSW PWROK when enabled */ + if (IS_ENABLED(CONFIG_CHIPSET_PP3300_RAIL_FIRST)) + enable_pp5000_rail(); + /* * Now wait for SLP_SUS_L to go high based on tPCH32. If this * signal doesn't go high within 250 msec then go back to G3. |