coil: CONFIG_SPI_MASTER->CONFIG_SPI_CONTROLLER

BUG=b:175244613
TEST=make buildall -j

Change-Id: I244ca864dad04f2b4f02bb1be2b482921da2fc88
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615123
Reviewed-by: Namyoon Woo <namyoon@chromium.org>

8 files changed, 24 insertions, 24 deletions

diff --git a/board/cr50/board.h b/board/cr50/board.h
index 6e139526b4..e91c228594 100644
--- a/board/cr50/board.h
+++ b/board/cr50/board.h
@@ -134,10 +134,10 @@
 /* Need to be able to bitbang the EC UART for updates through CCD. */
 #define CONFIG_UART_BITBANG
 
-/* Enable SPI Master (SPI) module */
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_MASTER_NO_CS_GPIOS
-#define CONFIG_SPI_MASTER_CONFIGURE_GPIOS
+/* Enable SPI controller (SPI) module */
+#define CONFIG_SPI_CONTROLLER
+#define CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
+#define CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS
 #define CONFIG_SPI_FLASH_PORT 0
 
 /* Enable SPI peripheral (SPP) module */
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
index e8849797d2..6b8b563314 100644
--- a/board/cr50/gpio.inc
+++ b/board/cr50/gpio.inc
@@ -310,7 +310,7 @@ PINMUX(GPIO(DETECT_SERVO),      B5, DIO_INPUT)
  *   DIOA12 = SPS_CS_L  (input)
  * The digital inputs are enabled in spp.c
  *
- * If CONFIG_SPI_MASTER is defined, these pads are used:
+ * If CONFIG_SPI_CONTROLLER is defined, these pads are used:
  *   DIOA4  = SPI_MOSI  (output)
  *   DIOA8  = SPI_CLK   (output)
  *   DIOA11 = SPI_MISO  (input)
diff --git a/board/host/board.c b/board/host/board.c
index 2ff24c7f2d..c531e00ec6 100644
--- a/board/host/board.c
+++ b/board/host/board.c
@@ -59,7 +59,7 @@ const struct i2c_port_t i2c_ports[] = {
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 #endif
 
-#ifdef CONFIG_SPI_MASTER
+#ifdef CONFIG_SPI_CONTROLLER
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
 };
diff --git a/board/host/board.h b/board/host/board.h
index e104872a14..c42d0e0536 100644
--- a/board/host/board.h
+++ b/board/host/board.h
@@ -74,7 +74,7 @@ enum {
 #define PD_MIN_POWER_MW       7500
 
 /* Configuration for fake Fingerprint Sensor */
-#define CONFIG_SPI_MASTER
+#define CONFIG_SPI_CONTROLLER
 #define CONFIG_SPI_FP_PORT    1 /* SPI1: third master config */
 
 /* UART indexes (use define rather than enum to expand them) */
diff --git a/chip/g/build.mk b/chip/g/build.mk
index 621ab6c1b0..e9e4d885a5 100644
--- a/chip/g/build.mk
+++ b/chip/g/build.mk
@@ -59,7 +59,7 @@ endif
 endif
 chip-$(CONFIG_DCRYPTO)+= dcrypto/x509.o
 
-chip-$(CONFIG_SPI_MASTER)+=spi_master.o
+chip-$(CONFIG_SPI_CONTROLLER)+=spi_master.o
 
 chip-y+= jitter.o
 chip-y+= pmu.o
diff --git a/chip/g/spi_master.c b/chip/g/spi_master.c
index 96acfa4315..90ad033e46 100644
--- a/chip/g/spi_master.c
+++ b/chip/g/spi_master.c
@@ -84,10 +84,10 @@ int spi_transaction(const struct spi_device_t *spi_device,
 	/* Copy the txdata into the 128B Transmit Buffer. */
 	memmove((uint8_t *)GREG32_ADDR_I(SPI, port, TX_DATA), txdata, txlen);
 
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
+#ifndef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
 	/* Drive chip select low. */
 	gpio_set_level(spi_device->gpio_cs, 0);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
+#endif  /* CONFIG_SPI_CONTROLLER_NO_CS_GPIOS */
 
 	/* Initiate the transaction. */
 	GWRITE_FIELD_I(SPI, port, ISTATE_CLR, TXDONE, 1);
@@ -116,10 +116,10 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		rxlen);
 
 err_cs_high:
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
+#ifndef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
 	/* Drive chip select high. */
 	gpio_set_level(spi_device->gpio_cs, 1);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
+#endif  /* CONFIG_SPI_CONTROLLER_NO_CS_GPIOS */
 
 	/* Release the port's mutex. */
 	mutex_unlock(&spi_mutex[port]);
@@ -162,20 +162,20 @@ int spi_enable(int port, int enable)
 		int spi_device_found = 0;
 		uint8_t max_div = 0;
 
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
+#ifndef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
 		gpio_config_module(MODULE_SPI, 1);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
+#endif  /* CONFIG_SPI_CONTROLLER_NO_CS_GPIOS */
 		for (i = 0; i < spi_devices_used; i++) {
 			if (spi_devices[i].port != port)
 				continue;
 
 			spi_device_found = 1;
 
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
+#ifndef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
 			/* Deassert CS# */
 			gpio_set_flags(spi_devices[i].gpio_cs, GPIO_OUTPUT);
 			gpio_set_level(spi_devices[i].gpio_cs, 1);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
+#endif  /* CONFIG_SPI_CONTROLLER_NO_CS_GPIOS */
 
 			/* Find the port's largest DIV (lowest frequency). */
 			if (spi_devices[i].div > max_div)
@@ -222,11 +222,11 @@ int spi_enable(int port, int enable)
 			if (spi_devices[i].port != port)
 				continue;
 
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
+#ifndef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
 			/* Make sure CS# is deasserted and disabled. */
 			gpio_set_level(spi_devices[i].gpio_cs, 1);
 			gpio_set_flags(spi_devices[i].gpio_cs, GPIO_ODR_HIGH);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
+#endif  /* CONFIG_SPI_CONTROLLER_NO_CS_GPIOS */
 		}
 
 		/* Disable passthrough. */
@@ -246,7 +246,7 @@ static void spi_init(void)
 {
 	size_t i;
 
-#ifdef CONFIG_SPI_MASTER_CONFIGURE_GPIOS
+#ifdef CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS
 	/* Set SPI_MISO as an input */
 	GWRITE_FIELD(PINMUX, DIOA11_CTL, IE, 1); /* SPI_MISO */
 #endif
diff --git a/chip/g/spi_master.h b/chip/g/spi_master.h
index 42441886f8..16af19f562 100644
--- a/chip/g/spi_master.h
+++ b/chip/g/spi_master.h
@@ -4,8 +4,8 @@
  * found in the LICENSE file.
  */
 
-#ifndef __CROS_EC_INCLUDE_SPI_MASTER_H
-#define __CROS_EC_INCLUDE_SPI_MASTER_H
+#ifndef __CROS_EC_INCLUDE_SPI_CONTROLLER_H
+#define __CROS_EC_INCLUDE_SPI_CONTROLLER_H
 
 #include "spi.h"
 
diff --git a/include/config.h b/include/config.h
index c335e757f8..3f184be58f 100644
--- a/include/config.h
+++ b/include/config.h
@@ -3153,7 +3153,7 @@
 #undef CONFIG_SPI_NOR_SMART_ERASE
 
 /* SPI master feature */
-#undef CONFIG_SPI_MASTER
+#undef CONFIG_SPI_CONTROLLER
 
 /* SPI master halfduplex/3-wire mode */
 #undef CONFIG_SPI_HALFDUPLEX
@@ -3162,11 +3162,11 @@
 #undef CONFIG_STM32_SPI1_MASTER
 
 /* SPI master configure gpios on init */
-#undef CONFIG_SPI_MASTER_CONFIGURE_GPIOS
+#undef CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS
 
 /* Support SPI masters without GPIO-specified Chip Selects, instead rely on the
  * SPI master port's hardwired CS pin. */
-#undef CONFIG_SPI_MASTER_NO_CS_GPIOS
+#undef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
 
 /* Support testing SPI periph interface driver. */
 #undef CONFIG_SPP_TEST