diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-06-14 09:28:25 -0500 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-06-14 16:16:09 -0700 |
| commit | 17e9c06a1a5f730343d1342e4a9f87739340ac93 (patch) | |
| tree | dde59e6eeee3b190e68aaef08134b1918870face | |
| parent | 7884ae482187ed79bde3bc0cd28bb22b2b7dfe6a (diff) | |
| download | chrome-ec-17e9c06a1a5f730343d1342e4a9f87739340ac93.tar.gz | |
haswell: Add notes about PL6 weirdness
It was found that PL6 behaves in an inverted way when it is
configured as open drain. Add notes about determining why this
is. Apparently PL6 is an oddity w.r.t. the other pins.
BUG=chrome-os-partner:19811
BRANCH=None
TEST=built
Change-Id: I2d5b27f49c4e51ba4eb75cda9c798b9a5793f767
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58679
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
| -rw-r--r-- | board/falco/board.c | 2 | ||||
| -rw-r--r-- | board/peppy/board.c | 2 | ||||
| -rw-r--r-- | board/slippy/board.c | 2 | ||||
| -rw-r--r-- | common/x86_power_haswell.c | 7 |
4 files changed, 10 insertions, 3 deletions
diff --git a/board/falco/board.c b/board/falco/board.c index 0bca002f49..60f431a794 100644 --- a/board/falco/board.c +++ b/board/falco/board.c @@ -98,6 +98,8 @@ const struct gpio_info gpio_list[GPIO_COUNT] = { {"PCH_NMI_L", LM4_GPIO_F, (1<<2), GPIO_OUT_HIGH, NULL}, {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL}, {"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL}, + /* FIXME: Why is PL6 act like it is inverted. Setting value to + * 0 makes the signal high, and setting it to 1 makes the signal low. */ {"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_ODR_LOW, NULL}, {"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL}, {"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL}, diff --git a/board/peppy/board.c b/board/peppy/board.c index fccb3aab8c..4e397a0f72 100644 --- a/board/peppy/board.c +++ b/board/peppy/board.c @@ -98,6 +98,8 @@ const struct gpio_info gpio_list[GPIO_COUNT] = { {"PCH_NMI_L", LM4_GPIO_F, (1<<2), GPIO_OUT_HIGH, NULL}, {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL}, {"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL}, + /* FIXME: Why is PL6 act like it is inverted. Setting value to + * 0 makes the signal high, and setting it to 1 makes the signal low. */ {"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_ODR_LOW, NULL}, {"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL}, {"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL}, diff --git a/board/slippy/board.c b/board/slippy/board.c index 56b499ad31..046669053c 100644 --- a/board/slippy/board.c +++ b/board/slippy/board.c @@ -98,6 +98,8 @@ const struct gpio_info gpio_list[GPIO_COUNT] = { {"PCH_NMI_L", LM4_GPIO_F, (1<<2), GPIO_OUT_HIGH, NULL}, {"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL}, {"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL}, + /* FIXME: Why is PL6 act like it is inverted. Setting value to + * 0 makes the signal high, and setting it to 1 makes the signal low. */ {"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_ODR_LOW, NULL}, {"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL}, {"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL}, diff --git a/common/x86_power_haswell.c b/common/x86_power_haswell.c index b6759da087..06bce3f204 100644 --- a/common/x86_power_haswell.c +++ b/common/x86_power_haswell.c @@ -239,9 +239,10 @@ void chipset_reset(int cold_reset) /* * Pulse must be at least 16 PCI clocks long = 500 ns. The gpio - * pin used by the EC is configured as open drain. Therefore, - * the driving RCIN# low needs to the level 1 to enable the - * FET and 0 to disable the FET. */ + * pin used by the EC is configured as open drain. However, + * empirically it was deteremined the polarity of the pin is + * inverted. No idea why. Therefore, the driving RCIN# low + * needs to be set to level 1. FIXME: why? */ gpio_set_level(GPIO_PCH_RCIN_L, 1); udelay(10); gpio_set_level(GPIO_PCH_RCIN_L, 0); |