diff options
| author | David Hendricks <dhendrix@chromium.org> | 2012-05-04 14:49:30 -0700 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2012-05-04 15:00:55 -0700 |
| commit | bd6b3267f068f7d7f6add68904ec0a290b20c8c1 (patch) | |
| tree | 9fea69a2bdab234eb9616e11ec1fe455cdc9bc77 | |
| parent | 391925a1cbc1d8087e2087781ee01cc2862461fc (diff) | |
| download | chrome-ec-bd6b3267f068f7d7f6add68904ec0a290b20c8c1.tar.gz | |
stm32f: Fix clock_init
0b00 for bits 1:0 (system clock switch) indicates HSI, 0b01
indicates HSE. Also, bit 23 is reserved (maybe it was just
a copying error from earlier).
BUG=None
TEST=Compiled and run on Snow
Change-Id: Ie6891492ae6e7e3bd30e4d7b183b156de1290fe0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
| -rw-r--r-- | chip/stm32/clock-stm32f100.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/stm32/clock-stm32f100.c b/chip/stm32/clock-stm32f100.c index 803695b227..bbe4a63e33 100644 --- a/chip/stm32/clock-stm32f100.c +++ b/chip/stm32/clock-stm32f100.c @@ -35,14 +35,14 @@ int clock_init(void) * no MCO => PLLCLK = 16 Mhz */ BUILD_ASSERT(CPU_CLOCK == 16000000); - STM32_RCC_CFGR = 0x00880001; + STM32_RCC_CFGR = 0x00080000; /* Enable the PLL */ STM32_RCC_CR |= 1 << 24; /* Wait for the PLL to lock */ while (!(STM32_RCC_CR & (1 << 25))) ; /* switch to SYSCLK to the PLL */ - STM32_RCC_CFGR = 0x00880002; + STM32_RCC_CFGR = 0x00080002; /* wait until the PLL is the clock source */ while ((STM32_RCC_CFGR & 0xc) != 0x8) ; |