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| author | Gerrit <chrome-bot@google.com> | 2012-05-04 16:18:33 -0700 |
|---|---|---|
| committer | Gerrit Code Review <gerrit@gerrit.golo.chromium.org> | 2012-05-04 16:18:33 -0700 |
| commit | 89502792891c25189b1bb465e0169dc3dd627907 (patch) | |
| tree | 7a2c797f519bdeef34a3c8efa9019ac71d474baa | |
| parent | 4daea3c1ab45c902e535adfb0a141b77eb9c2f1a (diff) | |
| parent | bd6b3267f068f7d7f6add68904ec0a290b20c8c1 (diff) | |
| download | chrome-ec-89502792891c25189b1bb465e0169dc3dd627907.tar.gz | |
Merge "stm32f: Fix clock_init"
| -rw-r--r-- | chip/stm32/clock-stm32f100.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/stm32/clock-stm32f100.c b/chip/stm32/clock-stm32f100.c index 803695b227..bbe4a63e33 100644 --- a/chip/stm32/clock-stm32f100.c +++ b/chip/stm32/clock-stm32f100.c @@ -35,14 +35,14 @@ int clock_init(void) * no MCO => PLLCLK = 16 Mhz */ BUILD_ASSERT(CPU_CLOCK == 16000000); - STM32_RCC_CFGR = 0x00880001; + STM32_RCC_CFGR = 0x00080000; /* Enable the PLL */ STM32_RCC_CR |= 1 << 24; /* Wait for the PLL to lock */ while (!(STM32_RCC_CR & (1 << 25))) ; /* switch to SYSCLK to the PLL */ - STM32_RCC_CFGR = 0x00880002; + STM32_RCC_CFGR = 0x00080002; /* wait until the PLL is the clock source */ while ((STM32_RCC_CFGR & 0xc) != 0x8) ; |