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Files:
TypeId0x55_SplTable_Prod_CZN_Chrome.sbin - SPL for Guybrush
Files:
APCB_CZN_D4.bin - Data only - No license, ABI or Version #
2022-03-21:
- Increase the number of SPD slots in APCB_CZN_D4.bin from 4 to 16
Slots 0 - 3:
lp4x-spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A
lp4x-spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F
lp4x-spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1
lp4x-spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B
Slots 4 - 15:
Place holder SPDs from Majolica
2021-04-05:
- Fix UMAmode
- Enable VBL/PSP to control eDP VDD.
2021-03-19:
- Remove all debug output
2021-03-18:
- Update DRQ routing
2021-03-11: Initial drop:
- Add APCB_CZN_D4.bin
This is a data file that gives configuration data to AMD's ABL,
the PSP AGESA Bootloader. As there is no code, there is no ABI,
license, or version number.
Specified contents describing memory initialization:
Memory is 2 channel, LPDDR4x
The GPIOs to use for the SPD identifiers:
Bit 0: GPIO 109
Bit 1: GPIO 87
Bit 2: GPIO 75
Bit 3: GPIO 88
SPDs from the guybrush platform:
lp4x-spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A
lp4x-spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F
lp4x-spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1
All other GPIO IDs are unused.
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