AMD Merlin Falcon: remove build warnings

1. Add const in PCIe_COMPLEX_DESCRIPTOR and EarlyOemGpioTable
The warnings are assignment discards 'const' qualifier in
src/mainboard/amd/bettong/BiosCallOuts.c and
src/mainboard/amd/bettong/PlatformGnbPcie.c
2. Change AltImageBasePtr and ImageBasePtr to VOID *
AltImageBasePtr and ImageBasePtr are two fields in AMD_CONFIG_PARAMS.
In orininal AGESA these two fiels are UINT32. This will result build
warning in agesawrapper_amdinitpost:
AmdParamStruct.StdHeader.AltImageBasePtr = NULL;
So change these two according to Steppe Eagle and Bald Eagle.

I also change the header files in binary PI code and rebuild AGESA.bin.
The new AGESA.bin is the same as befor, so I didn't upload AGESA.bin.

Change-Id: I59cf8b1bc0dc15c001f7b3ba0a5a945374663908
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>

4 files changed, 15 insertions, 7 deletions

diff --git a/pi/amd/00660F01/AGESA.h b/pi/amd/00660F01/AGESA.h
index a47e14f..17205b1 100644
--- a/pi/amd/00660F01/AGESA.h
+++ b/pi/amd/00660F01/AGESA.h
@@ -610,8 +610,8 @@ typedef struct {
                                                            * @li @b Bit31 - last descriptor in topology
                                                            */
   IN       UINT32               SocketId;                 ///< Socket Id
-  IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
-  IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       const PCIe_PORT_DESCRIPTOR *PciePortList;      ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       const PCIe_DDI_DESCRIPTOR  *DdiLinkList;       ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
   IN       VOID                 *Reserved;                ///< Reserved for future use
 } PCIe_COMPLEX_DESCRIPTOR;
 
@@ -828,7 +828,7 @@ mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mF
 {mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
 {mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration}}
 #define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
-{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}, 0, 0}
+{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0}
 #define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
 {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0}
 #define  PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \
@@ -1002,7 +1002,7 @@ typedef struct {
 
 /// GNB configuration info
 typedef struct {
-  IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+  IN       const PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
                                                         * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
                                                         * Example of topology definition for single socket system:
                                                         * @code
diff --git a/pi/amd/00660F01/AMD.h b/pi/amd/00660F01/AMD.h
index 16e51f1..319d9a0 100644
--- a/pi/amd/00660F01/AMD.h
+++ b/pi/amd/00660F01/AMD.h
@@ -175,9 +175,9 @@ typedef enum {
 /// The standard header for all AGESA services.
 /// For internal AGESA naming conventions, see @ref amdconfigparamname .
 typedef struct {
-  IN       UINT32          ImageBasePtr;     ///< The AGESA Image base address.
+  IN       VOID *          ImageBasePtr;     ///< The AGESA Image base address.
   IN       UINT32          Func;             ///< The service desired
-  IN       UINT32          AltImageBasePtr;  ///< Alternate Image location
+  IN       VOID *          AltImageBasePtr;  ///< Alternate Image location
   IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
   IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
   IN       UINT64          HeapBasePtr;      ///< Location of the heap
diff --git a/pi/amd/00660F01/FP4/AGESA_Release_Notes.txt b/pi/amd/00660F01/FP4/AGESA_Release_Notes.txt
index 5a04239..2892cd9 100644
--- a/pi/amd/00660F01/FP4/AGESA_Release_Notes.txt
+++ b/pi/amd/00660F01/FP4/AGESA_Release_Notes.txt
@@ -5,6 +5,14 @@
 
 =============================================================================
 AGESA PI Version:  1.0.0.7                 Test Board: Bettong Alfa
+Binary PI version: 1.2                     Binary PI Build Date: May 29 2015
+=============================================================================
+1. Update header files.
+     Update header files according commit d82006ea
+2. The AGESA.bin is the same as Binary PI version 1.1
+
+=============================================================================
+AGESA PI Version:  1.0.0.7                 Test Board: Bettong Alfa
 Binary PI version: 1.1                     Binary PI Build Date: May 29 2015
 =============================================================================
 1. Update to CarrizoPI version 1.0.0.7
diff --git a/pi/amd/00660F01/Proc/Fch/Common/FchCommonCfg.h b/pi/amd/00660F01/Proc/Fch/Common/FchCommonCfg.h
index 0e7341c..fb2bae2 100644
--- a/pi/amd/00660F01/Proc/Fch/Common/FchCommonCfg.h
+++ b/pi/amd/00660F01/Proc/Fch/Common/FchCommonCfg.h
@@ -1322,7 +1322,7 @@ typedef struct _FCH_RESET_DATA_BLOCK {
   BOOLEAN               QeEnabled;                      /// Quad Mode Enabled
   BOOLEAN               FchOscout1ClkContinous;         ///< FCH OSCOUT1_CLK Continous
   UINT8                 LpcClockDriveStrength;          ///< Lpc Clock Drive Strength
-  VOID*                 EarlyOemGpioTable;              /// Pointer of Early OEM GPIO table
+  const VOID*           EarlyOemGpioTable;              /// Pointer of Early OEM GPIO table
 //  VOID*                 OemSpiDeviceTable;              /// Pointer of OEM Spi Device table
 } FCH_RESET_DATA_BLOCK;