soc/mediatek/mt8192: Add dram.elf for DRAM full calibration

Add the DRAM full calibration binary 'dram.elf' to train the DDR.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I0b1db9f3dbd36d261cfcb04994d2dbb6a8838f35

5 files changed, 99 insertions, 0 deletions

diff --git a/soc/mediatek/mt8192/README.md b/soc/mediatek/mt8192/README.md
new file mode 100644
index 0000000..8357521
--- /dev/null
+++ b/soc/mediatek/mt8192/README.md
@@ -0,0 +1,74 @@
+# Firmware list
+- drame.elf
+
+--------------------------------------------------------------------------------
+# `dram.elf` Introduction
+
+`dram.elf` is one ELF format file which is used for calibration.
+The dram.elf is loaded at the first time bootup, it will do DRAM
+full calibration, and save calibration parameters to NAND (or EMMC)
+for faster bootup after the frist bootup.
+
+## Who uses it
+   - coreboot loads `dram.elf` at the first time bootup if no DRAM parameters exist.
+
+## How to load `dram.elf`
+   - coreboot locates `dram.elf` file, and locates the entry point "_start",
+     then it passes DRAM struct "param", and call _start(&param) to execute `dram.elf`
+     flow.
+
+## Parameters
+```
+    struct dramc_param {
+        struct dramc_param_header header; // see below
+        void (*do_putc)(unsigned char c);
+        struct dramc_data dramc_datas;    // see below
+    };
+```
+   Below shows the internal structure of dramc_param:
+```
+    struct dramc_param_header {
+        u32 checksum;   /* checksum of dramc_datas, update in the coreboot */
+        u16 version;    /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */
+        u16 size;       /* size of whole dramc_param, update in the coreboot */
+        u16 status;     /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */
+        u16 flags;      /* DRAMC_PARAM_FLAGS, update in the dram blob */
+    };
+
+    struct dramc_data {
+        struct ddr_base_info ddr_info;
+        struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
+    };
+
+    struct ddr_base_info {
+        u16 config_dvfs;		/* DRAMC_PARAM_DVFS_FLAG */
+        u16 ddr_type;			/* DRAMC_PARAM_DDR_TYPE */
+        u16 ddr_geometry;		/* DRAMC_PARAM_GEOMETRY_TYPE */
+        u16 voltage_type;		/* DRAM_PARAM_VOLTAGE_TYPE */
+        u32 support_ranks;
+        u64 rank_size[RANK_MAX];
+        struct emi_mdl emi_config;
+        dram_cbt_mode cbt_mode[RANK_MAX];
+    };
+
+    struct sdram_params {
+        u32 rank_num;
+        u16 num_dlycell_perT;
+        u16 delay_cell_timex100;
+
+    /* duty */
+    s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
+    s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+    s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
+        .......
+        .......
+    };
+```
+
+## The output of `dram.elf`
+   - `dram.elf` will set the suitable dramc settings, also save the DRAM parameters
+     to NAND (or EMMC) on the specified section: "RW_DDR_TRAINING".
+
+## Return Values
+   - 0   : means successful.
+   - < 0 : means failed.
diff --git a/soc/mediatek/mt8192/dram.elf b/soc/mediatek/mt8192/dram.elf
new file mode 100644
index 0000000..684963b
--- /dev/null
+++ b/soc/mediatek/mt8192/dram.elf
diff --git a/soc/mediatek/mt8192/dram.elf.md5 b/soc/mediatek/mt8192/dram.elf.md5
new file mode 100644
index 0000000..44782b4
--- /dev/null
+++ b/soc/mediatek/mt8192/dram.elf.md5
@@ -0,0 +1 @@
+32b68e6af2fc9844b643a4be249278a9 *dram.elf
diff --git a/soc/mediatek/mt8192/dram_release_notes.txt b/soc/mediatek/mt8192/dram_release_notes.txt
new file mode 100644
index 0000000..e6e13bd
--- /dev/null
+++ b/soc/mediatek/mt8192/dram_release_notes.txt
@@ -0,0 +1,15 @@
+# 2020.09.16
+
+1. Built from Chrome OS 13473.0.2020_09_16_2253.
+2. Include changes:
+
+eed9075 dramc: MT8192: Use clear data rate log format
+c57d520 dramc: MT8192: Adjust vcore voltage to correct value for DDR calibration
+a3651f6 pmic: MT6359: Allow to modify VGPU11 voltage
+bdff3f3 dramc: MT8192: Update the output message for easy debug
+824f1e0 dramc: MT8192: Load correct emi setting by the ddr geometry
+f488694 dramc: MT8192: Save the dramc params result after calibration
+adab87d dramc: MT8192: Update the dramc param struct
+3a1c53e dramc: MT8192: Update the dram control drivers
+a87ece6 dramc: MT8192: Add RX gating fast calibration flow
+c112bf9 dramc: MT8192: Add DRAM full calibration blob source code
diff --git a/soc/mediatek/mt8192/license.txt b/soc/mediatek/mt8192/license.txt
new file mode 100644
index 0000000..6886c61
--- /dev/null
+++ b/soc/mediatek/mt8192/license.txt
@@ -0,0 +1,9 @@
+MediaTek Inc. grants permission to use and redistribute aforementioned firmware
+files for the use with devices containing MediaTek chipsets, but not as part of
+the Linux kernel or in any other form which would require these files themselves
+to be covered by the terms of the GNU General Public License or the GNU Lesser
+General Public License.
+
+These firmware files are distributed in the hope that they will be useful, but
+are provided WITHOUT ANY WARRANTY, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTY
+OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.