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* fix(tree): correct some typosElyes Haouas2023-05-091-1/+1
| | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
* refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash2023-03-151-1/+1
| | | | | | | | | | | | | | | | | | | BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
* Merge changes from topic "panic_cleanup" into integrationBipin Ravi2023-02-231-2/+2
|\ | | | | | | | | | | | | | | | | * changes: refactor(bl31): use elx_panic for sysreg_handler64 refactor(aarch64): rename do_panic and el3_panic refactor(aarch64): remove weak links to el3_panic refactor(aarch64): refactor usage of elx_panic refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage
| * refactor(aarch64): rename do_panic and el3_panicGovindraj Raja2023-02-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | Current panic call invokes do_panic which calls el3_panic, but now panic handles only panic from EL3 anid clear separation to use lower_el_panic() which handles panic from lower ELs. So now we can remove do_panic and just call el3_panic for all panics. Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | build: always prefix section names with `.`Chris Kay2023-02-201-1/+1
|/ | | | | | | | | | | | | | | | | Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
* fix(ras): restrict RAS support for NS worldManish Pandey2022-11-081-1/+1
| | | | | | | | | | | | | | | Current RAS framework in TF-A only supports handling errors originating from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all lower Els. To make the current design of RAS explicit, rename this macro to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when switching to NS world. Note: I am unaware of any platform which traps errors originating in Secure world to EL3, if there is any such platform then it need to be explicitly implemented in TF-A Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750
* fix(rcar3): fix RPC-IF device node nameGeert Uytterhoeven2022-10-031-1/+1
| | | | | | | | | | | | | | | According to the Generic Names Recommendation in the Devicetree Specification Release v0.3, and the DT Bindings for the Renesas Reduced Pin Count Interface, the node name for a Renesas RPC-IF device should be "spi". The node name matters, as the node is enabled by passing a DT fragment from TF-A to subsequent software. Fix this by renaming the device node in the passed DT fragment from "rpc" to "spi". Fixes: 12c75c8886a0ee69 ("feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Change-Id: Idb43353947607611331abc344f8c8ae932a20408
* refactor(renesas): remove mbedtls_common makefile inclusionManish V Badarkhe2022-09-071-1/+0
| | | | | | | | | Renesas platform does not support crypto, but mbedtls_common.mk is still included in its makefile. Therefore, this inclusion was removed to avoid un-necessary compilation of mbedTLS source. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib6978255e39a7f5d5013952841930ae68b12c318
* Merge changes I25047322,Id476f815 into integrationManish Pandey2022-01-312-7/+10
|\ | | | | | | | | | | * changes: fix(plat/rcar3): change stack size of BL31 fix(plat/rcar3): fix SYSTEM_OFF processing for R-Car D3
| * fix(plat/rcar3): change stack size of BL31Takuya Sakata2022-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | Increase the stack size to avoid stack overflow when the LOG_LEVEL compile option is set high. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I25047322763bff148dba13848a3a40f4c7cf90b7
| * fix(plat/rcar3): fix SYSTEM_OFF processing for R-Car D3Takuya Sakata2022-01-221-6/+9
| | | | | | | | | | | | | | | | | | | | Fixed an issue where the CPU and Cluster could not be turned OFF when the SYSTEM_OFF has executed. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Id476f815b58246ae0574c04ccb3eb201d09039b9
* | refactor(renesas): disable CRYPTO_SUPPORT optionManish V Badarkhe2022-01-111-1/+6
|/ | | | | | | | | Disabled CRYPTO_SUPPORT option for Renesas platform as it does not follow the TF-A authentication mechanism where Trusted-Boot mandates Crypto module support. Change-Id: I3aa771e983e3dde083dd8a861f25c0714ffd707f Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3Takuya Sakata2021-12-121-1/+1
| | | | | | | | | | Update the revision number in the revision management file. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I19f713de68e62a2ed3f4ec08c31b35af6a4014ef
* feat(plat/rcar3): modify type for Internal function argumentTakuya Sakata2021-12-121-6/+6
| | | | | | | | | | | Modify the type of the variable that stores the value for MPIDR in the internal function from uint64_t to u_register_t. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46
* feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53Takuya Sakata2021-12-122-2/+3
| | | | | | | | | | | | | Add new function so that the value of bit at WUPMSKCA57/53, which points to CPU other than the BOOT CPU, is 1 at initialization. Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is basically 0 and target bit value is changed to 1 only when CPU_OFF. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914
* fix: libc: use long for 64-bit types on aarch64Scott Branden2021-11-082-3/+7
| | | | | | | | | Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width types for such change. Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1 Signed-off-by: Scott Branden <scott.branden@broadcom.com>
* feat(plat/rcar): change process for Suspend To RAMToshiyuki Ogasahara2021-10-161-6/+14
| | | | | | | | | | | | - Added the function rcar_pwr_domain_pwr_down_wfi() for power down process. And change the sequence to power down. - Removed clearing the count of psci_locks (PSCI exclusive lock) during Warm Boot. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I684d54a798a6dccde15fbebe16c6e104cbb470ed
* feat(plat/rcar3): keep RWDT enabledMarek Vasut2021-09-121-6/+6
| | | | | | | In case the WDT is enabled by prior stage, keep it enabled. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie7c0eaf2f59dd8c30a9ef686a7000424f38d6352
* feat(plat/rcar3): modify LifeC register setting for R-Car D3Toshiyuki Ogasahara2021-09-121-6/+6
| | | | | | | | | Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I3f173ac44c11743965c013ef238748b0dc8cabab
* feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3Toshiyuki Ogasahara2021-09-121-20/+2
| | | | | | | | | | | Because the Realtime module stop control register n (RMSTPCRn) are not supported in R-Car D3. Therefore, remove access to these registers in R-Car D3. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I4647e28d0e176ff97151e9842019ba12cefe5c03
* feat(plat/rcar3): add process of SSCG setting for R-Car D3Toshiyuki Ogasahara2021-09-121-1/+1
| | | | | | | | | | | | - Added the condition where output the SSCG (MD12) setting to log for R-Car D3. - Added the process to switching the bit rate of SCIF by the SSCG (MD12) setting value for R-Car D3. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9
* feat(plat/rcar3): add process to back up X6 and X7 register's valueToshiyuki Ogasahara2021-09-121-1/+5
| | | | | | | | | | Because the x6 and x7 registers will be overwritten by the callee function, added the processing the register's value push to/pop from stack memory. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I5351a008d3b208a30a8bc8651b8d9b4d1a02a8e8
* feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_upToshiyuki Ogasahara2021-09-121-0/+2
| | | | | | | | | | Added the process of SYSECEXTMASK bit set/clear for following power Resume/Shutoff flow. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b
* feat(plat/rcar3): change the memory map for OP-TEEToshiyuki Ogasahara2021-09-121-2/+2
| | | | | | | | | The memory area size of OP-TEE was changed from 1MB to 2MB because the size of OP-TEE has increased. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ic8a165c83a3a9ef2829f68d5fabeed9ccb6da95e
* feat(plat/rcar3): use PRR cut to determine DRAM size on M3Toshiyuki Ogasahara2021-09-121-7/+14
| | | | | | | | | | | The new M3 DRAM size can be determined by the PRR cut version. Read the PRR cut version, and if it is older than cut 30, use legacy DRAM size scheme, else report 8GB in 2GBx4 2ch split. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # Fix DRAM size judgment by PRR register, reword commit message Change-Id: Ib83176d0d09cab5cae0119ba462e42c66c642798
* feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537Toshiyuki Ogasahara2021-09-121-0/+2
| | | | | | | | | | Apply ERRATA_A53_1530924 and ERRATA_A57_1319537. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # Drop Makefile header change, reword commit message Change-Id: I7d6e7e40bad6545a1d96470ce1a6e2d04e042670
* fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3Toshiyuki Ogasahara2021-09-121-3/+0
| | | | | | | | | Fix disabling MFIS write protection for R-Car D3. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I8bb5787c09c53dff55d6de89adfcb71157533976
* fix(plat/rcar3): fix eMMC boot support for R-Car D3Toshiyuki Ogasahara2021-09-121-4/+0
| | | | | | | | | | Fix to support of booting from eMMC (50MHz x 8) on Draak board for R-Car D3. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I0ab2b5c7f8075acbf5f4a69694fb535dddc1a4c8
* fix(plat/rcar3): fix version judgment for R-Car D3Toshiyuki Ogasahara2021-09-122-0/+10
| | | | | | | | | Added the process of judgment and logging for R-Car D3 Ver.1.1 and Ver.1.0. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I326aa42374b70b6a4a71893561a7eaa0b6eddef0
* fix(plat/rcar3): fix source file to make about GICv2Toshiyuki Ogasahara2021-09-121-4/+3
| | | | | | | | | | Changed the plat/renesas/common/common.mk to change the source files about GICv2 by include gicv2.mk, because gic_common.c has deprecated. Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Iaa7eae6b2c1dd79a05339325e6bc422d87bce49e
* refactor(plat/ea_handler): Use default ea handler implementation for panicPali Rohár2021-08-131-5/+1
| | | | | | | | | | | | | Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and panic, so it can be called also from overwritten / weak function plat_ea_handler() implementation. Replace every custom implementation of printing verbose error message of external aborts in custom plat_ea_handler() functions by a common implementation from plat_default_ea_handler() function. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
* feat(plat/rcar3): emit RPC status to DT fragment if RPC unlockedMarek Vasut2021-07-101-0/+30
| | | | | | | | | In case the RCAR_RPC_HYPERFLASH_LOCKED is 0, emit DT node /soc/rpc@ee200000 with property status = "okay" into the DT fragment passed to subsequent software, to indicate the RPC is unlocked. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id93c4573ab1c62cf13fa5a803dc5818584a2c13a
* feat(plat/rcar3): add a DRAM size setting for M3NToshiyuki Ogasahara2021-07-101-0/+5
| | | | | | | | | This commit adds a DRAM size setting when building with RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Ib7fea862ab2e0bcafaf39ec030384f0fddda9b96
* feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0Toshiyuki Ogasahara2021-07-101-2/+2
| | | | | | | | Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I44b9e5a992e8a44cfeafad6d2c1a97aa59baca4e
* feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCBToshiyuki Ogasahara2021-07-101-0/+6
| | | | | | | | Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286
* fix(drivers/rcar3): fix CPG registers redefinitionToshiyuki Ogasahara2021-07-103-7/+11
| | | | | | | | This commit deletes the value of the redefined CPG register. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
* fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0Marek Vasut2021-07-101-4/+32
| | | | | | | | | | | | | | | The DRAM channel 0 memory area in 32bit space is limited to 2 GiB window. Furthermore, the first 128 MiB of this memory window are reserved and not accessible by the system software, hence the 32bit area memory node is limited to range 0x4800_0000..0xbfff_ffff. In case there are more than 2 GiB of DRAM populated in channel 0, it is necessary to generate two memory nodes, once covering the 2 GiB - 128 MiB area in the 32bit space, and another covering the rest of the memory in 64bit space. This patch implements handling of such a case. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I3495241fb938e355352e817afaca8f01d04c81d2
* refactor(plat/rcar3): factor out DT memory node generationMarek Vasut2021-07-101-28/+40
| | | | | | | | | | Move the code that adds single new memory@ node into the DT fragment passed to system software into separate function. Adjust the failure message to be more specific and print the address range of node which failed to be added. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie42cd7756b045271f070bca93c524fff6238f5a2
* feat(plat/rcar3): add optional support for gzip-compressed BL33Marek Vasut2021-07-103-3/+46
| | | | | | | | | | | | | | | The BL33 size on this platform is limited to 1 MiB, add optional support for decompressing and starting gzip-compressed BL33, which may help with this size limitation. This functionality is disabled by default, set RCAR_GEN3_BL33_GZIP=1 during build to enable it. The BL33 at 0x50000000 should then be gzip compressed, however if the BL33 does not have a valid gzip header, it is copied to the correct location and started as-is, this is a fallback for legacy systems and systems which update to gzip-compressed BL33. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Id93f1c7e6f17db1ffb952ea086562993473f6efa
* renesas: rzg: Add support to identify EK874 RZ/G2E boardLad Prabhakar2021-04-203-5/+75
| | | | | | | | Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
* drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoCLad Prabhakar2021-04-201-0/+2
| | | | | | | | | DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the same. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
* renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N boardLad Prabhakar2021-04-203-4/+41
| | | | | | | | Add support to identify HopeRun HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce
* drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoCLad Prabhakar2021-04-201-0/+2
| | | | | | | | Add support for initializing DRAM on RZ/G2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
* renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H boardLad Prabhakar2021-04-203-5/+58
| | | | | | | | Add support to identify HopeRun HiHope RZ/G2H board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970
* drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoCLad Prabhakar2021-04-201-0/+2
| | | | | | | | Add support for initializing DRAM on RZ/G2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
* drivers: renesas: rzg: Switch using common ddr codeLad Prabhakar2021-04-202-5/+8
| | | | | | | | | Switch using common ddr driver code from renesas/common/ddr directory for RZ/G2M SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
* drivers: renesas: ddr: Move to commonLad Prabhakar2021-04-201-3/+3
| | | | | | | | | Move ddr driver code to common directory, so that the same code can be re-used by both R-Car Gen3 and RZ/G2 platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727
* plat: renesas: rzg: DT memory node enhancementsBiju Das2021-01-131-24/+48
| | | | | | | | | Add DT node support for channel 0 where physical memory is split between 32bit space and 64bit space. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I99a18dbb14cdb54100a836c16445242e430794e3
* plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board supportBiju Das2021-01-134-4/+1114
| | | | | | | | | | | | | | The HiHope RZ/G2M board from HopeRun consists of main board (HopeRun HiHope RZ/G2M main board) and sub board(HopeRun HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: I3ed55aa4a2cc5c9d9cd6440e087bcd93186520c7
* plat: renesas: common: Include ulcb_cpld.h conditionallyBiju Das2021-01-131-0/+2
| | | | | | | | | Include header ulcb_cpld.h in plat_pm.c only if RCAR_GEN3_ULCB is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Change-Id: Ie89223097c608265c50e32778e8df28feed82480
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