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* refactor(ras): replace RAS_EXTENSION with FEAT_RASManish Pandey2023-05-095-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds. FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well. This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH. Proper support for KFH will be added in future patches. BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
* Merge changes I9d06e0ee,I6980e84f into integrationManish Pandey2023-05-037-7/+68
|\ | | | | | | | | | | * changes: feat(tegra): implement 'pwr_domain_off_early' handler feat(psci): introduce 'pwr_domain_off_early' hook
| * feat(tegra): implement 'pwr_domain_off_early' handlerVarun Wadekar2023-04-267-7/+68
| | | | | | | | | | | | | | | | | | | | | | | | This patch implements the pwr_domain_off_early handler for Tegra platforms. Powering off the boot core on some Tegra platforms is not allowed and the SOC specific helper functions for Tegra194, Tegra210 and Tegra186 implement this restriction. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I9d06e0eee12314764adb0422e023a5bec6ed9c1e
* | fix(tegra): remove dependency on CPU registers to get boot parametersKalyani Chidambaram Vaidyanathan2023-04-301-12/+7
|/ | | | | | | | | | | | | | | | Commit 3e14df6f6 removed the code to clear the CPU registers X0 - X3, which affected the Tegra platforms. Tegra platforms rely on the boot parameters passed through custom mechanisms and do not use these general purpose registers, but maintained sanity checks to support legacy bootloaders. These sanity checks went out of sync due to the code cleanup from bl31_entrypoint(). This patch removes the checks and calls the SOC specific handlers to retrieve the boot parameters. Change-Id: I0cf4d9c0370c33ff7715b48592b6bc0602f3c93e Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Merge "fix(tegra): append major revision to the chip_id value" into integrationVarun Wadekar2023-03-131-3/+5
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| * fix(tegra): append major revision to the chip_id valueVarun Wadekar2023-03-091-3/+5
| | | | | | | | | | | | | | | | | | This patch appends the chip's major revision to the chip id value to form the SoC version value expected by the SMCCC_GET_SOC_VERSION function ID. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I09118f446f6b8198588826d4a161bd97dcb6a581
* | Merge "style: remove useless trailing semicolon and line continuations" into ↵Manish Pandey2023-03-135-7/+7
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| * | style: remove useless trailing semicolon and line continuationsElyes Haouas2023-03-095-7/+7
| |/ | | | | | | | | | | | | | | | | found using checkpatch.pl[1] [1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c
* | fix(tegra210): support legacy SMC_ID 0xC2FEFE00Kalyani Chidambaram Vaidyanathan2023-03-091-2/+3
|/ | | | | | | | This patch introduces a workaround to support the legacy SMC FID 0xC2FEFE00 to maintain compatibility with older software components. Change-Id: Icf2ef9cfa6b28c09bbab325a642d0b3b20b23535 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
* Merge "fix: remove useless "return" at void functions" into integrationMadhukar Pappireddy2023-02-231-1/+0
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| * fix: remove useless "return" at void functionsElyes Haouas2023-02-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | void functions() returns nothing. So remove useless "return". found using checkpatch.pl[1] [1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl Change-Id: I3daab2abec225a657af48f7d8c215cc554713074 Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
* | build: always prefix section names with `.`Chris Kay2023-02-202-11/+11
|/ | | | | | | | | | | | | | | | | Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
* fix: remove old-style declarationsBoyan Karatotev2022-12-011-3/+3
| | | | | | | | TF-A wants to eventually enable -Wold-style-definition globally. Convert the rare few instances where this is still the case. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I9c450fc875cf097e6de2ed577ea3b085821c9f5e
* fix(ras): restrict RAS support for NS worldManish Pandey2022-11-081-1/+1
| | | | | | | | | | | | | | | Current RAS framework in TF-A only supports handling errors originating from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all lower Els. To make the current design of RAS explicit, rename this macro to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when switching to NS world. Note: I am unaware of any platform which traps errors originating in Secure world to EL3, if there is any such platform then it need to be explicitly implemented in TF-A Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750
* fix(tegra194/ras): remove incorrect erxctlr assertVarun Wadekar2022-03-211-7/+1
| | | | | | | | | | | The ERXCTLR_EL1 register reads are RES0 for some error records leading to a false assert on a read back. This patch removes the assert on reading back the ERXCTLR_EL1 register to fix this issue. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I0cab30b12656a800ba87b8bb94b4c67a2331dee6
* fix: libc: use long for 64-bit types on aarch64Scott Branden2021-11-085-9/+18
| | | | | | | | | Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width types for such change. Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1 Signed-off-by: Scott Branden <scott.branden@broadcom.com>
* build(fdt-wrappers): introduce FDT wrappers makefileChris Kay2021-10-261-3/+5
| | | | | | | | | | | This has been introduced to simplify dependencies on the FDT wrappers. We generally want to avoid pulling in components on a file-by-file basis, particularly as we are trying to draw conceptual boxes around components in preparation for transitioning the build system to CMake, where dependencies are modelled on libraries rather than files. Signed-off-by: Chris Kay <chris.kay@arm.com> Change-Id: Idb7ee05a9b54a8caa3e07f36e608867e20b6dcd5
* refactor(tegra132): deprecate platformVarun Wadekar2021-08-168-731/+2
| | | | | | | | | | | The Tegra132 platforms have reached their end of life and are no longer used in the field. Internally and externally, all known programs have removed support for this legacy platform. This change removes this platform from the Tegra tree as a result. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a
* refactor(plat/ea_handler): Use default ea handler implementation for panicPali Rohár2021-08-131-4/+1
| | | | | | | | | | | | | Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and panic, so it can be called also from overwritten / weak function plat_ea_handler() implementation. Replace every custom implementation of printing verbose error message of external aborts in custom plat_ea_handler() functions by a common implementation from plat_default_ea_handler() function. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
* refactor(plat/nvidia): use SOC_ID definesYann Gautier2021-05-271-4/+5
| | | | | | | Use the macros that are now defined in include/lib/smccc.h. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ibe3c17acd2482b7779318c8a922a138dcace5554
* plat/nvidia: tegra: Rename SMC APIManish V Badarkhe2020-11-191-2/+2
| | | | | | | | Renamed SMC API from "plat_smccc_feature_available" to "plat_is_smccc_feature_available" as per the current implementation. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib0fa400816fba61039c2029a9e127501a6a36811
* Merge "Don't return error information from console_flush" into integrationMark Dykes2020-10-142-12/+12
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| * Don't return error information from console_flushJimmy Brisson2020-10-092-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Remove deprecated macro from TF-A codeManish V Badarkhe2020-10-122-6/+6
|/ | | | | | | Removed '__ASSEMBLY__' deprecated macro from TF-A code Change-Id: I9082a568b695acb5b903f509db11c8672b62d9d0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* Merge changes from topic "ehf_common" into integrationManish Pandey2020-09-183-29/+6
|\ | | | | | | | | | | * changes: plat: tegra: Use generic ehf defines ehf: use common priority level enumuration
| * plat: tegra: Use generic ehf definesSandeep Tripathy2020-09-103-29/+6
| | | | | | | | | | | | | | | | Use common ehf file for generic frameworks like SDEI, RAS and extend plat specific defines using 'PLAT_EHF_DESC'. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: I8a8161c6030f8d226a8bdf0301e7fe6139f019a4
* | Tegra: common: fixup the bl31 code size to be copied at resetanzhou2020-08-311-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | If the CPU doesn't run from BL31_BASE, the firmware needs to be copied from load address to BL31_BASE during cold boot. The size should be the actual size of the code, which is indicated by the __RELA_END__ linker variable. This patch updates the copy routine to use this variable as a result. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: Ie3a48dd54cda1dc152204903d609da3117a0ced9
* | Tegra: common: disable GICC after domain offanzhou2020-08-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | The the GIC CPU interface should be disabled after cpu off. The Tegra power management code should mark the connected core as asleep as part of the CPU off sequence. This patch disables the GICC after CPU off as a result. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea
* | Tegra: platform specific BL31_SIZEanzhou2020-08-315-1/+20
| | | | | | | | | | | | | | | | | | This patch moves the BL31_SIZE to the Tegra SoC specific tegra_def.h. This helps newer platforms configure the size of the memory available for BL31. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82
* | Tegra186: sanity check power state typeVarun Wadekar2020-08-311-0/+5
| | | | | | | | | | | | | | | | | | | | This patch sanity checks the power state type before use, from the platform's PSCI handler. Verified with TFTF Standard Test Suite. Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Tegra: fixup CNTPS_TVAL_EL1 delay timer readsanzhou2020-08-311-4/+2
| | | | | | | | | | | | | | | | | | | | | | The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical, decrementing timer as the source. The current logic incorrectly marks this as an incrementing timer, by negating the timer value. This patch fixes the anomaly and updates the driver to remove this logic. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4
* | Tegra: add platform specific 'runtime_setup' handlerKalyani Chidambaram Vaidyanathan2020-08-316-24/+119
| | | | | | | | | | | | | | | | | | Tegra SoCs would like the flexibility to perform chip specific actions before we complete cold boot. This patch introduces a platform specific 'runtime_setup' handler to provide that flexibility. Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
* | Tegra: remove ENABLE_SVE_FOR_NS = 0Kalyani Chidambaram Vaidyanathan2020-08-311-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The SVE CPU extension library reads the id_aa64pfr0_el1 register to check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for pre-8.2 platforms, but this flag can safely be enabled now that the library can enable the feature at runtime. This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0" as a result. Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
* | Tegra194: remove unused tegra_mc_defs headerVarun Wadekar2020-08-273-689/+0
| | | | | | | | | | | | | | | | | | This patch removes the unused header from the Tegra194 platform files. As a result, the TSA MMIO would be removed from the memory map too. Change-Id: I2d38b3da7a119f5dfd6cfd429e481f4e6ad3481e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Tegra: memctrl: platform setup handler functionsVarun Wadekar2020-08-276-235/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | The driver initially contained the setup steps to help Tegra186 and Tegra194 SoCs. In order to support future SoCs and make sure that the driver remains generic enough, some code should be moved to SoC. This patch creates a setup handler for a platform to implement its initialization sequence. Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Tegra194: memctrl: remove streamid security cfg registersPritesh Raithatha2020-08-271-146/+0
| | | | | | | | | | | | | | | | | | The stream ID security configuration settings shall be done by the previous level bootloader. This change removes the same settings from the Tegra194 platform code as a result. Change-Id: Ia170ca4c2119db8f1d0251f1c193add006f81004 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
* | Tegra194: memctrl: remove streamid override cfg registersPritesh Raithatha2020-08-271-248/+0
| | | | | | | | | | | | | | | | | | The stream ID override configuration is saved during System Suspend as part MB1 bct. This change removes the same support from the Tegra194 platform code as a result. Change-Id: I4c19dc0d8b29190908673fb5ed7ed892af8906ab Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
* | Tegra: debug prints indicating SC7 entry sequence completionVarun Wadekar2020-08-271-7/+8
| | | | | | | | | | | | | | | | | | | | This patch adds prints to display the completion of System Suspend programming sequence for Tegra platforms. The console needs to be kept alive until the very end of the System Suspend sequence as a result. Change-Id: I8e0e2054a272665d0a067bb894dda1605a9d2eb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Tegra194: add strict checking mode verificationAnthony Zhou2020-08-274-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | After enabling the strict checking mode, verify that the strict mode has really been enabled by querying the MCE. If the mode is found to be disabled, the code should assert. Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
* | Tegra194: memctrl: update TZDRAM base at 1MB granularityVarun Wadekar2020-08-271-2/+4
| | | | | | | | | | | | | | | | | | The Memory controller expects the TZDRAM base value at 1MB granularity and the current driver does not respect that limitation. This patch fixes that anomaly. Change-Id: I6b72270f331ba5081e19811df4a78623e457341a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Tegra194: ras: split up RAS error clear SMC call.David Pu2020-08-273-10/+107
| | | | | | | | | | | | | | | | | | | | | | In order to make sure SMC call is within 25us, this patch reduces number of RAS errors accessed to 8 at most for each SMC call and takes a input/output parameter to specify in progress RAS error record index. The measured SMC call latency is about 20us under Linux test kernel driver. Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f Signed-off-by: David Pu <dpu@nvidia.com>
* | Tegra: platform specific GIC sourcesVarun Wadekar2020-08-275-6/+10
| | | | | | | | | | | | | | | | | | | | | | The TEGRA_GICv2_SOURCES contains the list of GIC sources required to compile the GICv2 support for platforms. This patch includes the TEGRA_GICv2_SOURCES macro from individual makefiles to allow future platforms to use suport for GICv3. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I429b1a0c7764ab370675f873a50cecda871110cb
* | Tegra194: add memory barriers during DRAM to SysRAM copyVarun Wadekar2020-08-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds memory barriers to the trampoline code copying TZDRAM contents to SysRAM during exit from System Suspend. These barriers make sure that all the copies go through before we start executing in SysRAM. Reported by: Nathan Tuck <ntuck@nvidia.com> Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Tegra: sip: add VPR resize enabled checkAnthony Zhou2020-08-276-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Memory Controller provides a control register to check if the video memory can be resized. The previous bootloader might have locked this feature, which will be reflected by this register. This patch reads the control register before processing a video memory resize request. An error code, -ENOTSUP, is returned if the feature is locked. Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
* | Tegra194: add redundancy checks for MMIO writesAnthony Zhou2020-08-275-1/+43
| | | | | | | | | | | | | | | | | | MMIO writes should verify that the writes actually went through. Read the value back after the write operation, perform assert if the read back value is not same as the write value. Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
* | Tegra: remove unused cortex_a53.hVarun Wadekar2020-08-272-3/+3
| | | | | | | | | | | | | | | | | | | | This patch removes the unused cortex_a53.h header file from common Tegra files. This change fixes the violation of CERTC Rule: DCL23. Change-Id: Iaf7c34cc6323b78028258e188c00724c52afba85 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Tegra194: report failure to enable dual executionKalyani Chidambaram Vaidyanathan2020-08-271-0/+6
| | | | | | | | | | | | | | | | | | During boot the platform enables dual execution for Xavier CPUs. This patch reads back the ACTLR_ELx register to verify that the bit is actually set. It asserts if the bit is not set. Change-Id: I5ba9491ced86285d307b95efa647a427ff77c79e Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
* | Tegra194: verify firewall settings before resource useKalyani Chidambaram Vaidyanathan2020-08-272-0/+66
|/ | | | | | | | | | | | | | The firewall settings for the hardware resources are present in the Security Configuration Registers. The firewall settings are programmed by other software components and so must be verified for correctness before touching the hardware resources they protect. This patch reads the firewall settings during early boot and asserts if the settings mismatch. Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Merge changes from topic "tegra194-spmd" into integrationMadhukar Pappireddy2020-08-252-4/+17
|\ | | | | | | | | | | | | | | * changes: Tegra194: introduce support for `SPD=spmd` Tegra: introduce backend support to compile libfdt Tegra: disable signed comparison plat: common: include "bl_common.h" from plat_spmd_manifest.c
| * Tegra194: introduce support for `SPD=spmd`Varun Wadekar2020-08-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the following changes to enable compilation for `SPD=spmd` command line option. * compile plat_spmd_manifest.c * compile libfdt source files Verified with the `SPD=spmd` command line option for Tegra194 platforms. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I7f57aa4f1756b19f78d87415bb80794417174bc8
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