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author | Manish Pandey <manish.pandey2@arm.com> | 2023-03-13 12:34:21 +0100 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-03-13 12:34:21 +0100 |
commit | 521d4fe6761ce62f06acf2b07248d8d5b5366ea3 (patch) | |
tree | 76356fb1804cb3502d7219826add272903430edf /plat/nvidia/tegra | |
parent | 404e835c33f676fefa8857c01365318b514cd1fd (diff) | |
parent | 9a90d720b8a027f11dc2d1b316f5df5318b0d367 (diff) | |
download | arm-trusted-firmware-521d4fe6761ce62f06acf2b07248d8d5b5366ea3.tar.gz |
Merge "style: remove useless trailing semicolon and line continuations" into integration
Diffstat (limited to 'plat/nvidia/tegra')
-rw-r--r-- | plat/nvidia/tegra/drivers/flowctrl/flowctrl.c | 2 | ||||
-rw-r--r-- | plat/nvidia/tegra/drivers/pmc/pmc.c | 2 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t186/drivers/mce/ari.c | 4 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c | 4 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_smmu.c | 2 |
5 files changed, 7 insertions, 7 deletions
diff --git a/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c b/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c index 8f5555459..4c9f4afc4 100644 --- a/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c +++ b/plat/nvidia/tegra/drivers/flowctrl/flowctrl.c @@ -84,7 +84,7 @@ static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr) void tegra_fc_ccplex_pgexit_lock(void) { unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; - uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;; + uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING; uint32_t icept_cpu_flags[] = { INTERCEPT_EXIT_PG_CORE0, INTERCEPT_EXIT_PG_CORE1, diff --git a/plat/nvidia/tegra/drivers/pmc/pmc.c b/plat/nvidia/tegra/drivers/pmc/pmc.c index 6c5a73baf..e70e7a6c1 100644 --- a/plat/nvidia/tegra/drivers/pmc/pmc.c +++ b/plat/nvidia/tegra/drivers/pmc/pmc.c @@ -103,7 +103,7 @@ void tegra_pmc_lock_cpu_vectors(void) bool tegra_pmc_is_last_on_cpu(void) { int i, cpu = read_mpidr() & MPIDR_CPU_MASK; - uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);; + uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); bool status = true; /* check if this is the last standing CPU */ diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c index a57bc11b9..6414e07e6 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c @@ -372,8 +372,8 @@ int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en * StandbyWFI or the equivalent signal, and always keeping the IDLE * voltage/frequency request register enabled. */ - val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ - ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ + val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) | + ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) | ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); return ari_request_wait(ari_base, 0U, diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c index cbc9aa3a6..1a4856324 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c @@ -246,8 +246,8 @@ int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en * StandbyWFI or the equivalent signal, and always keeping the IDLE * voltage/frequency request register enabled. */ - val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ - ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ + val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) | + ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) | ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val); diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index 310e95104..710d5c53e 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -24,7 +24,7 @@ static uint32_t tegra_misc_read_32(uint32_t off) uint32_t plat_get_num_smmu_devices(void) { uint32_t ret_num = MAX_NUM_SMMU_DEVICES; - uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \ + uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> BOARD_SHIFT_BITS) & BOARD_MASK_BITS); if (board_revid == BOARD_SYSTEM_FPGA_BASE) { |