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path: root/plat/nvidia/tegra/include/t186
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* Remove deprecated macro from TF-A codeManish V Badarkhe2020-10-121-2/+2
* Tegra: platform specific BL31_SIZEanzhou2020-08-311-0/+5
* Tegra: memctrl: platform setup handler functionsVarun Wadekar2020-08-271-1/+114
* Tegra: sip: add VPR resize enabled checkAnthony Zhou2020-08-271-0/+2
* Tegra186: system resume from TZSRAM memoryVarun Wadekar2020-03-181-4/+1
* Tegra186: disable PROGRAMMABLE_RESET_ADDRESSVarun Wadekar2020-03-181-1/+0
* Tegra: smmu: remove context save sequencePritesh Raithatha2020-03-112-4/+4
* Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194Varun Wadekar2020-03-111-0/+6
* Tegra186: add SE support to generate SHA256 of TZRAMJeetesh Burman2020-03-091-0/+10
* Tegra186: add support for bpmp_ipc driverJeetesh Burman2020-03-091-0/+15
* Tegra: per-SoC DRAM base valuesVarun Wadekar2020-01-311-0/+7
* Tegra: platform dependent address space sizesSteven Kao2019-01-311-1/+7
* Tegra: SiP: set GPU in reset after vpr resizeJeetesh Burman2019-01-311-0/+2
* Tegra186: save system suspend entry marker to TZDRAMVarun Wadekar2019-01-231-0/+1
* Tegra186: helper functions for CPU rst handler and SMMU ctx offsetVarun Wadekar2019-01-231-0/+1
* Tegra: rename secure scratch register macrosSteven Kao2019-01-231-0/+10
* Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1Varun Wadekar2019-01-231-0/+14
* Tegra: memctrl_v2: allow CPU accesses to TZRAMSteven Kao2019-01-231-1/+5
* Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCHHarvey Hsieh2019-01-231-1/+0
* Tegra: memctrl_v2: platform handlers to program MSSPuneet Saxena2019-01-231-0/+285
* Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LOHarvey Hsieh2019-01-181-0/+4
* Tegra: fix defects flagged by MISRA Rule 10.3Anthony Zhou2019-01-181-1/+1
* Tegra: common: drivers: fix MISRA defectsAnthony Zhou2019-01-181-3/+3
* Tegra: gpcdma: driver for general purpose DMAVarun Wadekar2019-01-181-0/+7
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-041-1/+1
* Standardise header guards across codebaseAntonio Nino Diaz2018-11-081-3/+3
* Tegra: memctrl: check GPU reset state from common placeVarun Wadekar2017-06-141-0/+2
* Tegra: add explicit casts for integer macrosVarun Wadekar2017-06-141-134/+122
* Use SPDX license identifiersdp-arm2017-05-031-25/+1
* Tegra: memctrl_v2: zero out NS Video memory carveout regionVarun Wadekar2017-05-011-23/+23
* Tegra: memmap Tegra micro-seconds timer controllerSteven Kao2017-05-011-0/+1
* Tegra: smmu: support for multiple devicesPritesh Raithatha2017-04-131-1/+1
* Tegra: memctrl_v2: remove non-secure access to TZSRAM memoryHarvey Hsieh2017-04-071-2/+0
* Tegra186: read activity monitor's clock counter valuesVarun Wadekar2017-04-071-1/+7
* Tegra186: move smmu driver to tegra/commonVarun Wadekar2017-04-071-0/+2
* Tegra186: move TSA macros to tegra_def.hVarun Wadekar2017-04-051-0/+37
* Tegra: drivers: memctrl: move chip specific defines to tegra_def.hVarun Wadekar2017-04-051-0/+39
* Tegra186: move platform specific MCE defines to tegra_def.hVarun Wadekar2017-04-051-0/+30
* Tegra: memctrl_v2: save TZDRAM settings to secure scratch registersHarvey Hsieh2017-04-051-0/+3
* Tegra186: use helper functions to get major/minor versionVarun Wadekar2017-03-301-4/+0
* Tegra186: handlers to get BL31 arguments from previous bootloaderVarun Wadekar2017-03-301-0/+2
* Tegra: memctrl_v2: TZRAM aperture configuration settingsVarun Wadekar2017-03-301-1/+1
* Tegra186: Enable ECC and Parity Protection for A02p SKUsVarun Wadekar2017-03-301-0/+7
* Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)Varun Wadekar2017-03-271-2/+0
* Tegra186: enable support for simulation environmentVarun Wadekar2017-03-231-3/+5
* Tegra186: re-configure MSS' client settingsVarun Wadekar2017-03-231-0/+5
* Tegra186: implement support for System SuspendVarun Wadekar2017-03-221-0/+14
* Tegra186: register FIQ interrupt sourcesVarun Wadekar2017-03-201-1/+9
* Tegra: memctrl_v2: implement MC txn override WARVarun Wadekar2017-03-201-0/+4
* Tegra186: support for C6/C7 CPU_SUSPEND statesVarun Wadekar2017-03-201-3/+15
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