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* fix(tree): correct some typosElyes Haouas2023-05-0913-16/+16
| | | | | | | found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
* Merge changes from topic "assert_boolean_set" into integrationManish Pandey2023-05-091-14/+1
|\ | | | | | | | | | | | | | | | | | | * changes: build!: check boolean flags are not empty fix(build): add a default value for INVERTED_MEMMAP fix(a5ds): add default value for ARM_DISABLE_TRUSTED_WDOG fix(st-crypto): move flag control into source code fix(stm32mp1): always define PKA algos flags fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF
| * fix(st-crypto): move flag control into source codeLionel Debieve2023-05-031-14/+1
| | | | | | | | | | | | | | | | Remove the control from the include file to avoid compilation issue. Add the check in the source code instead. Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Change-Id: I533f829607f76389399a3e8dbc3c6095278562ab
* | feat(tc): allow secure watchdog timer to trigger periodicallyMadhukar Pappireddy2023-05-042-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: 1. Configures SBSA secure watchdog timer as Group0 interrupt for TC platform while keeping it as Group1 secure interrupt for other CSS based SoCs. 2. Programs the watchdog timer to trigger periodically 3. Provides a Group0 interrupt handler for TC platform port to deactivate the EL3 interrupt due to expiry of secure watchdog timer and refresh it explicitly. Change-Id: I3847d6eb7347c6ea0e527b97b096119ca1e6701b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | feat(sbsa): helper api for refreshing watchdog timerMadhukar Pappireddy2023-05-041-2/+8
| | | | | | | | | | | | | | | | | | | | This patch adds a helper API to explicitly refresh SBSA secure watchdog timer. Please refer section A.3 of the following spec: https://developer.arm.com/documentation/den0029/latest/ Change-Id: I2d0943792aea0092bee1e51d74b908348587e66b Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge changes from topic "mp/group0_support" into integrationOlivier Deprez2023-05-031-2/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: docs(spm): support for handling Group0 interrupts feat(spmd): introduce platform handler for Group0 interrupt feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI feat(spmd): register handler for group0 interrupt from NWd
| * | feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABIMadhukar Pappireddy2023-05-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When Group0 Secure interrupts in secure world get trapped to S-EL2 SPMC, FFA_EL3_INTR_HANDLE ABI is invoked by SPMC to delegate interrupt handling to EL3 firmware (i.e., SPMD). SPMD further delegates to platform handler which successfully handles the Group0 secure interrupt before returning control to SPMC. Change-Id: I8cc0fec20803b96c81582910ad2668e38b167fb8 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | Merge changes I9d06e0ee,I6980e84f into integrationManish Pandey2023-05-031-0/+2
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: feat(tegra): implement 'pwr_domain_off_early' handler feat(psci): introduce 'pwr_domain_off_early' hook
| * | feat(psci): introduce 'pwr_domain_off_early' hookVarun Wadekar2023-04-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the 'pwr_domain_off_early' hook for platforms wanting to perform housekeeping steps before the PSCI framework starts the CPU power off sequence. Platforms might also want to use ths opportunity to ensure that the CPU off sequence can proceed. The PSCI framework expects a return code of PSCI_E_DENIED, if the platform wants to halt the CPU off sequence. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I6980e84fc4d6cb80537a178d0d3d26fb28a13853
* | | Merge "feat(el3-runtime): handle traps for IMPDEF registers accesses" into ↵Manish Pandey2023-05-021-0/+3
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| * | feat(el3-runtime): handle traps for IMPDEF registers accessesVarun Wadekar2023-04-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces support to handle traps from lower ELs for IMPDEF system register accesses. The actual support is left to the platforms to implement. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5
* | | Merge "fix(ras): do not put RAS check before esb macro" into integrationManish V Badarkhe2023-04-281-2/+3
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| * | | fix(ras): do not put RAS check before esb macroManish Pandey2023-04-271-2/+3
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Macro esb used in TF-A executes the instruction "esb" and is kept under RAS_EXTENSION macro. RAS_EXTENSION, as it stands today, is only enabled for platforms which wants RAS errors to be handled in Firmware while esb instruction is available when RAS architecture feature is present irrespective of its handling. Currently TF-A does not have mechanism to detect whether RAS is present or not in HW, define this macro unconditionally. Its harmless for non-RAS cores as this instruction executes as NOP. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I556f2bcf5669c378bda05909525a0a4f96c7b336
* | | feat(sme): enable SME2 functionality for NS worldJayanth Dodderi Chidanand2023-04-272-1/+22
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_SME2 is an extension of FEAT_SME and an optional feature from v9.2. Its an extension of SME, wherein it not only processes matrix operations efficiently, but also provides outer-product instructions to accelerate matrix operations. It affords instructions for multi-vector operations. Further, it adds an 512 bit architectural register ZT0. This patch implements all the changes introduced with FEAT_SME2 to ensure that the instructions are allowed to access ZT0 register from Non-secure lower exception levels. Additionally, it adds support to ensure FEAT_SME2 is aligned with the existing FEATURE DETECTION mechanism, and documented. Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKEDAndre Przywara2023-04-253-13/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we only support FEAT_DIT to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_DIT=2), by splitting is_armv8_4_dit_present() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed). We use ENABLE_DIT in two occassions in assembly code, where we just set the DIT bit in the DIT system register. Protect those two cases by reading the CPU ID register when ENABLE_DIT is set to 2. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I506d352f18e23c60db8cdf08edb449f60adbe098 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "feat(gcs): support guarded control stack" into integrationBipin Ravi2023-04-254-1/+35
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| * | feat(gcs): support guarded control stackMark Brown2023-04-184-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm v9.4 introduces support for Guarded Control Stack, providing mitigations against some forms of RPO attacks and an efficient mechanism for obtaining the current call stack without requiring a full stack unwind. Enable access to this feature for EL2 and below, context switching the newly added EL2 registers as appropriate. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
* | | Merge changes from topic "mb/trusted-boot-update" into integrationSandrine Bailleux2023-04-242-40/+26
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: refactor(auth)!: unify REGISTER_CRYPTO_LIB refactor(auth): replace plat_convert_pk docs(auth): add auth_decrypt in CM chapter feat(auth): compare platform and certificate ROTPK for authentication docs(auth): add 'calc_hash' function's details in CM
| * | | refactor(auth)!: unify REGISTER_CRYPTO_LIBYann Gautier2023-04-211-36/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Have only one definition for REGISTER_CRYPTO_LIB macro, with all the possible fields. Worst case adds 4 u64 to crypto_lib_desc. While at it, correct some MISRA violations: MC3R1.R12.1: (advisory) The precedence of operators within expressions should be made explicit. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I1342a20e6eef2354753182c2a81ff959e03e5c81
| * | | refactor(auth): replace plat_convert_pkYann Gautier2023-04-212-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following discussions in the reviews of the patch that introduced plat_convert_pk() function [1], it was decided to deprecate it to avoid weak function declaration. A new optional function pointer convert_pk is added to crypto_lib_desc_t. A new function crypto_mod_convert_pk() will either call crypto_lib_desc.convert_pk() if it is defined, or do the same as what was done by the weak function otherwise. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17174 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I9358867f8bfd5e96b5ee238c066877da368e43c6
| * | | feat(auth): compare platform and certificate ROTPK for authenticationManish V Badarkhe2023-04-211-0/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Compared the full ROTPK with the ROTPK obtained from the certificate when the platform supports full ROTPK instead of hash of ROTPK. Additionally, changed the code to verify the ROTPK before relying on it for signature verification. Change-Id: I52bb9deb1a1dd5b184d3156bddad14c238692de7 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | | Merge "fix(uuid): add missing `#include` directives" into integrationManish Pandey2023-04-212-2/+7
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| * | fix(uuid): add missing `#include` directivesChris Kay2023-04-172-2/+7
| |/ | | | | | | | | | | | | These include directives were missing from both `uuid.h` files. Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | feat(fvp): add Event Log maximum size property in DTManish V Badarkhe2023-04-181-3/+5
|/ | | | | | | | | | | | Updated the code to get and set the 'tpm_event_log_max_size' property in the event_log.dtsi. In this change, the maximum Event Log buffer size allocated by BL1 is passed to BL2, rather than both relying on the maximum Event Log buffer size macro. Change-Id: I7aa6256390872171e362b6f166f3f7335aa6e425 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* Merge "feat(hcx): initialize HCRX_EL2 to its default value" into integrationManish Pandey2023-04-131-0/+8
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| * feat(hcx): initialize HCRX_EL2 to its default valueJuan Pablo Conde2023-04-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value of register HCRX_EL2 is UNKNOWN out of reset. This can affect the behavior in lower exception levels, such as traps to EL2 due to a wrong configuration of the register upon reset. This patch initializes the register at EL3 and disables all traps related to it. On the other hand, new fields have been introduced for HCRX_EL2, which are now defined in this patch, so they can be used in further development. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I0bf1e949aa0d3be9f227358ad088a1ecb96ce222
* | Merge "fix(rpi3): initialize SD card host controller" into integrationAndré Przywara2023-04-131-0/+3
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| * | fix(rpi3): initialize SD card host controllerRob Newberry2023-04-131-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial configuration parameters for Rasperry Pi 3's sdhost controller, and then configure and use those parameters. This change allows warm reboots of UEFI on Raspberry Pi 3B+ where existing code often fails with "unknown error". See discussion at: https://github.com/pftf/RPi3/issues/24 The basic idea is that some initial configuration parameters (clock rate, bus width) aren't configured into the hardware before commands start being sent. I suspect that the particular setting that matters is the "slow card" bit, but the initial clock setting also seemed wrong to me. Change-Id: I526def340def143f23f3422f1fc14c12c937ca7f Signed-off-by: Rob Newberry <robthedude@mac.com>
* | feat(pie/por): support permission indirection and overlayMark Brown2023-04-124-1/+117
|/ | | | | | | | | | | | | | | | | | | Arm v8.9 introduces a series of features providing a new way to set memory permissions. Instead of directly encoding the permissions in the page tables the PTEs contain indexes into an array of permissions stored in system registers, allowing greater flexibility and density of encoding. Enable access to these features for EL2 and below, context switching the newly added EL2 registers as appropriate. Since all of FEAT_S[12]P[IO]E are separately discoverable we have separate build time options for enabling them, but note that there is overlap in the registers that they implement and the enable bit required for lower EL access. Change the FVP platform to default to handling them as dynamic options so the right decision can be made by the code at runtime. Signed-off-by: Mark Brown <broonie@kernel.org> Change-Id: Icf89e444e39e1af768739668b505661df18fb234
* Merge "style(docs): fix typo s/flase/false/" into integrationJoanna Farley2023-04-062-2/+2
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| * style(docs): fix typo s/flase/false/Michal Simek2023-03-212-2/+2
| | | | | | | | | | | | | | Trivial typo fix. Change-Id: Ifac249d0110414ca71040a6d2a0b3e963480c1a9 Signed-off-by: Michal Simek <michal.simek@amd.com>
* | feat(cpus): add support for blackhawk cpuGovindraj Raja2023-04-041-0/+23
| | | | | | | | | | | | | | | | | | Add basic CPU library code to support the Blackhawk CPU, BlackHawk core is based out of Hunter ELP core, so overall library code was adapted based on that. Change-Id: I4750e774732218ee669dceb734cd107f46b78492 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | feat(cpus): add support for chaberton cpuGovindraj Raja2023-04-041-0/+23
| | | | | | | | | | | | | | | | | | Add basic CPU library code to support the Chaberton CPU, Chaberton cores are based out of Hunter core, so overall library code was adapted based on that. Change-Id: I58321c77f2c364225a764da6fa65656d1bec33f1 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* | feat(ethos-n)!: add protected NPU firmware setupMikael Olsson2023-04-041-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Arm(R) Ethos(TM)-N NPU driver is built with TZMP1 support, the NPU should use the firmware that has been loaded into the protected memory by BL2. The Linux Kernel NPU driver in the non-secure world is not allowed to configure the NPU to do this in a TZMP1 build so the SiP service will now configure the NPU to boot with the firmware in the protected memory. BREAKING CHANGE: The Linux Kernel NPU driver can no longer directly configure and boot the NPU in a TZMP1 build. The API version has therefore been given a major version bump with this change. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65d00f54b3ade3665d7941e270da7a3dec02281a
* | feat(ethos-n): add stream extends and attr supportMikael Olsson2023-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SiP service for the Arm(R) Ethos(TM)-N NPU driver will now handle setting up the address extension and attribute control for the NPU's streams. The non-secure world will still be allowed to read the address extension for stream0 but non-secure access to all other streams have been removed. The API version has been given a minor bump with this change to indicate the added functionality. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I2b041ca4a0a2b5cd6344a4ae144f75e137c72592
* | feat(ethos-n): add reserved memory address supportMikael Olsson2023-04-041-1/+2
| | | | | | | | | | | | | | | | | | The FCONF parsing of the HW_CONFIG for the Arm(R) Ethos(TM)-N NPU now supports reading the address of the reserved memory setup for the NPU so the address can be used in the SiP service for the NPU. Change-Id: I0968255a966e84896b00ea935d6aa3d5232c5f7b Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
* | feat(ethos-n): add event and aux control supportMikael Olsson2023-04-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The SiP service for the Arm(R) Ethos(TM)-N NPU driver will now handle setting up the NPU's event and aux control registers during the SMC reset call. The aux control register will no longer be accessible by the non-secure world. The API version has been given a minor bump with this change to indicate the added functionality. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I5b099e25978aa4089c384eb17c5060c5b4eaf373
* | feat(ethos-n): add SMC call to get FW propertiesMikael Olsson2023-04-041-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Arm(R) Ethos(TM)-N NPU firmware is loaded by BL2 into protected memory, the Linux kernel NPU driver cannot access the firmware. To still allow the kernel driver to access some information about the firmware, SMC calls have been added so it can check compatibility and get the necessary information to map the firmware into the SMMU for the NPU. The API version has been given a minor version bump with this change to indicate the added functionality. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: Idb076b7bcf54ed7e8eb39be80114dc1d1c45336d
* | feat(ethos-n): add check for NPU in SiP setupMikael Olsson2023-04-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The SiP service in the Arm(R) Ethos(TM)-N NPU driver requires that there is at least one NPU available. If there is no NPU available, the driver is either used incorrectly or the HW config is incorrect. To ensure that the SiP service is not incorrectly used, a setup handler has been added to the service that will validate that there is at least one NPU available. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I8139a652f265cfc0db4a37464f39f1fb92868e10
* | fix(ethos-n): add workaround for erratum 2838783Mikael Olsson2023-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | To workaround Arm(R) Ethos(TM)-N NPU erratum 2838783, the NPU has been configured to allow being woken up by both secure and non-secure events to make sure that an event always wakes up the NPU. The API version has been given a minor version bump with this change to indicate that this fix is included. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I429cdd6bf1e633b4dedf2e94af28937dd892a0ba
* | feat(ethos-n): add support for NPU to cert_createMohamed Elzahhar2023-04-042-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | Add Juno specific Makefile to the certificate tool build. That Makefile is included by the certificate tool Makefile to add information about the authentication data for the Arm(R) Ethos(TM)-N NPU's firmware binary. Signed-off-by: Mohamed Elzahhar <Mohamed.Elzahhar@arm.com> Signed-off-by: Rob Hughes <robert.hughes@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: Ie4b6a1c29d73b3ed5041b57f2cd88033be18a63a
* | feat(ethos-n): add NPU support in fiptoolDaniele Castro2023-04-041-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platform specific Makefile to add UUIDs and command options for the Arm(R) Ethos(TM)-N NPU firmware binary and certificate data to the FIP so that the TF-A's BL2 can later be used to load the Arm(R) Ethos(TM)-N NPU firmware binary into memory and verify its integrity. Add separate driver specific include header file for the Arm(R) Ethos(TM)-N NPU images containing UUIDs and command options to make it easy to port the FIP support to other platforms. Signed-off-by: Daniele Castro <daniele.castro@arm.com> Signed-off-by: Rob Hughes <robert.hughes@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I8cd64fb20d58f8bd539facb085606213d6cead05
* | feat(ethos-n): add NPU sleeping SMC callMikael Olsson2023-04-041-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The non-secure world delegation of the register needed to determine if the Arm(R) Ethos(TM)-N NPU is active or sleeping will be removed in the future. In preparation for the change, a new SMC call has been added to allow the non-secure world to ask the SiP service for the state instead. A minor API version bump has been done with this change to indicate support for the new functionality. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I1338341be385cf1891f4809efb7083fae6d928bc
* | feat(ethos-n): add reset type to reset SMC callsJoshua Pimm2023-04-041-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | Adds a reset type argument for the soft and hard reset SMC calls to indicate whether to perform a full reset and setup or only halt the Arm(R) Ethos(TM)-N NPU. For use in cases where the NPU will not be used but must be put into a known state, such as suspending the NPU as part of power management. Signed-off-by: Joshua Pimm <joshua.pimm@arm.com> Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I6018af85a28b0e977166ec29d26f04739123140c
* | fix(aarch64): allow build with ARM_ARCH_MINOR=4Andre Przywara2023-03-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building the FVP platform with SPMD (which activates the context switch code), but keeping ARM_ARCH_MINOR to 4 or lower, the assembler will complain about the SCXTNUM_EL2 system register not being supported by the "selected processor". Allow building this combination of options by defining the SCXTNUM_EL2 register via the generic S3_ encoding, so any assembler, with any -march settings, will generate the access without any warnings. We do protect accesses to this register by runtime checks, if not explicitly requested otherwise, so can override the toolchain in this case. Change-Id: I0941f4c4dcf541bd968c153b9c3fac61ca23f7ef Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-282-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SVE_FOR_NS=2), by splitting sve_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SVE specific setup. Change the FVP platform default to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I1caaba2216e8e2a651452254944a003607503216 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKEDJayanth Dodderi Chidanand2023-03-283-5/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for runtime detection (ENABLE_SME_FOR_NS=2), by splitting feat_sme_supported() into an ID register reading function and a second function to report the support status. That function considers both build time settings and runtime information (if needed), and is used before we do SME specific setup. Change the FVP platform default to the now supported dynamic option (=2),so the right decision can be made by the code at runtime. Change-Id: Ida9ccf737db5be20865b84f42b1f9587be0626ab Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* | Merge changes from topic "psci-osi" into integrationManish Pandey2023-03-283-2/+36
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: feat(sc7280): add support for PSCI_OS_INIT_MODE feat(fvp): enable support for PSCI OS-initiated mode feat(psci): update PSCI_FEATURES feat(psci): add support for OS-initiated mode feat(psci): add support for PSCI_SET_SUSPEND_MODE build(psci): add build option for OS-initiated mode docs(psci): add design proposal for OS-initiated mode
| * | feat(fvp): enable support for PSCI OS-initiated modeWing Li2023-03-231-0/+6
| | | | | | | | | | | | | | | Change-Id: I4cd6d2bd7ec7f581bd525d5323a3b54e855e2e51 Signed-off-by: Wing Li <wingers@google.com>
| * | feat(psci): update PSCI_FEATURESWing Li2023-03-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the PSCI_FEATURES handler to indicate support for OS-initiated mode per section 5.15.2 of the PSCI spec (DEN0022D.b) based on the value of `FF_SUPPORTS_OS_INIT_MODE`, which is conditionally enabled by the `PSCI_OS_INIT_MODE` build option. Change-Id: I5da8a989b53419ad2ab55b73ddeee6e882c25554 Signed-off-by: Wing Li <wingers@google.com>
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