diff options
author | Yann Gautier <yann.gautier@st.com> | 2022-11-14 14:14:48 +0100 |
---|---|---|
committer | Yann Gautier <yann.gautier@st.com> | 2022-11-14 14:14:48 +0100 |
commit | 981b9dcb878c868983388cd86c133f663eab1af4 (patch) | |
tree | bf8eea6827453d5f47807c31efd262b46d9f33d2 /plat/st/stm32mp1 | |
parent | c3170fd80b722cbd48a340a0a17f740b7676616c (diff) | |
download | arm-trusted-firmware-981b9dcb878c868983388cd86c133f663eab1af4.tar.gz |
refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE
The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.
Change-Id: I04452453ed84567b0de39e900594a81526562259
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'plat/st/stm32mp1')
-rw-r--r-- | plat/st/stm32mp1/bl2_plat_setup.c | 45 | ||||
-rw-r--r-- | plat/st/stm32mp1/include/platform_def.h | 20 | ||||
-rw-r--r-- | plat/st/stm32mp1/include/stm32mp1_private.h | 4 | ||||
-rw-r--r-- | plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c | 103 | ||||
-rw-r--r-- | plat/st/stm32mp1/plat_image_load.c | 16 | ||||
-rw-r--r-- | plat/st/stm32mp1/platform.mk | 44 | ||||
-rw-r--r-- | plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk | 2 | ||||
-rw-r--r-- | plat/st/stm32mp1/sp_min/sp_min_setup.c | 4 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1.S | 9 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1.ld.S | 16 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1_def.h | 4 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1_private.c | 27 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1_security.c | 136 | ||||
-rw-r--r-- | plat/st/stm32mp1/stm32mp1_stm32image_def.h | 78 |
14 files changed, 7 insertions, 501 deletions
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c index c64a618e2..4f04a6f03 100644 --- a/plat/st/stm32mp1/bl2_plat_setup.c +++ b/plat/st/stm32mp1/bl2_plat_setup.c @@ -164,14 +164,6 @@ void bl2_platform_setup(void) ERROR("DDR mapping: error %d\n", ret); panic(); } - -#if STM32MP_USE_STM32IMAGE -#ifdef AARCH32_SP_OPTEE - INFO("BL2 runs OP-TEE setup\n"); -#else - INFO("BL2 runs SP_MIN setup\n"); -#endif -#endif /* STM32MP_USE_STM32IMAGE */ } #if STM32MP15 @@ -226,19 +218,6 @@ void bl2_el3_plat_arch_setup(void) BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_SECURE); -#if STM32MP_USE_STM32IMAGE -#ifdef AARCH32_SP_OPTEE - mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, - STM32MP_OPTEE_SIZE, - MT_MEMORY | MT_RW | MT_SECURE); -#else - /* Prevent corruption of preloaded BL32 */ - mmap_add_region(BL32_BASE, BL32_BASE, - BL32_LIMIT - BL32_BASE, - MT_RO_DATA | MT_SECURE); -#endif -#endif /* STM32MP_USE_STM32IMAGE */ - /* Prevent corruption of preloaded Device Tree */ mmap_add_region(DTB_BASE, DTB_BASE, DTB_LIMIT - DTB_BASE, @@ -396,9 +375,7 @@ skip_console_init: stm32mp1_syscfg_enable_io_compensation_finish(); -#if !STM32MP_USE_STM32IMAGE fconf_populate("TB_FW", STM32MP_DTB_BASE); -#endif /* !STM32MP_USE_STM32IMAGE */ stm32mp_io_setup(); } @@ -414,7 +391,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) bl_mem_params_node_t *bl32_mem_params; bl_mem_params_node_t *pager_mem_params __unused; bl_mem_params_node_t *paged_mem_params __unused; -#if !STM32MP_USE_STM32IMAGE const struct dyn_cfg_dtb_info_t *config_info; bl_mem_params_node_t *tos_fw_mem_params; unsigned int i; @@ -426,12 +402,10 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) HW_CONFIG_ID, TOS_FW_CONFIG_ID, }; -#endif /* !STM32MP_USE_STM32IMAGE */ assert(bl_mem_params != NULL); switch (image_id) { -#if !STM32MP_USE_STM32IMAGE case FW_CONFIG_ID: /* Set global DTB info for fixed fw_config information */ set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, @@ -494,7 +468,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) } } break; -#endif /* !STM32MP_USE_STM32IMAGE */ case BL32_IMAGE_ID: if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { @@ -510,18 +483,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) paged_image_info = &paged_mem_params->image_info; } -#if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) - /* Set OP-TEE extra image load areas at run-time */ - pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; - pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; - - paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + - dt_get_ddr_size() - - STM32MP_DDR_S_SIZE - - STM32MP_DDR_SHMEM_SIZE; - paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; -#endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ - err = parse_optee_header(&bl_mem_params->ep_info, &pager_mem_params->image_info, paged_image_info); @@ -541,13 +502,11 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */ bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */ } else { -#if !STM32MP_USE_STM32IMAGE bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); assert(tos_fw_mem_params != NULL); bl_mem_params->image_info.image_max_size += tos_fw_mem_params->image_info.image_max_size; -#endif /* !STM32MP_USE_STM32IMAGE */ bl_mem_params->ep_info.args.arg0 = 0; } break; @@ -556,9 +515,9 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); assert(bl32_mem_params != NULL); bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; -#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT +#if PSA_FWU_SUPPORT stm32mp1_fwu_set_boot_idx(); -#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ +#endif /* PSA_FWU_SUPPORT */ break; default: diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h index fe4ef3d44..61b847f6a 100644 --- a/plat/st/stm32mp1/include/platform_def.h +++ b/plat/st/stm32mp1/include/platform_def.h @@ -25,26 +25,10 @@ #define PLATFORM_STACK_SIZE 0xC00 #endif -#if STM32MP_USE_STM32IMAGE -#ifdef AARCH32_SP_OPTEE -#define OPTEE_HEADER_IMAGE_NAME "teeh" -#define OPTEE_CORE_IMAGE_NAME "teex" -#define OPTEE_PAGED_IMAGE_NAME "teed" -#define OPTEE_HEADER_BINARY_TYPE U(0x20) -#define OPTEE_CORE_BINARY_TYPE U(0x21) -#define OPTEE_PAGED_BINARY_TYPE U(0x22) -#endif - -/* SSBL = second stage boot loader */ -#define BL33_IMAGE_NAME "ssbl" -#define BL33_BINARY_TYPE U(0x0) -#else /* STM32MP_USE_STM32IMAGE */ #define FIP_IMAGE_NAME "fip" #define METADATA_PART_1 "metadata1" #define METADATA_PART_2 "metadata2" -#endif /* STM32MP_USE_STM32IMAGE */ - #define STM32MP_PRIMARY_CPU U(0x0) #define STM32MP_SECONDARY_CPU U(0x1) @@ -81,7 +65,7 @@ /******************************************************************************* * BL32 specific defines. ******************************************************************************/ -#if STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) +#if defined(IMAGE_BL32) #if ENABLE_PIE #define BL32_BASE 0 #define BL32_LIMIT STM32MP_BL32_SIZE @@ -90,7 +74,7 @@ #define BL32_LIMIT (STM32MP_BL32_BASE + \ STM32MP_BL32_SIZE) #endif -#endif /* STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) */ +#endif /* defined(IMAGE_BL32) */ /******************************************************************************* * BL33 specific defines. diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h index 23934e92f..21ef60d0a 100644 --- a/plat/st/stm32mp1/include/stm32mp1_private.h +++ b/plat/st/stm32mp1/include/stm32mp1_private.h @@ -34,9 +34,5 @@ static inline void stm32mp1_syscfg_boot_mode_disable(void){} void stm32mp1_deconfigure_uart_pins(void); -#if STM32MP_USE_STM32IMAGE -uint32_t stm32mp_get_ddr_ns_size(void); -#endif /* STM32MP_USE_STM32IMAGE */ - void stm32mp1_init_scmi_server(void); #endif /* STM32MP1_PRIVATE_H */ diff --git a/plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c b/plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c deleted file mode 100644 index 4fce55a9e..000000000 --- a/plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <common/bl_common.h> -#include <common/desc_image_load.h> -#include <plat/common/platform.h> - -#include <platform_def.h> - -/******************************************************************************* - * Following descriptor provides BL image/ep information that gets used - * by BL2 to load the images and also subset of this information is - * passed to next BL image. The image loading sequence is managed by - * populating the images in required loading order. The image execution - * sequence is managed by populating the `next_handoff_image_id` with - * the next executable image id. - ******************************************************************************/ -static bl_mem_params_node_t bl2_mem_params_descs[] = { - /* Fill BL32 related information */ - { - .image_id = BL32_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | EXECUTABLE | EP_FIRST_EXE), - - /* Updated at runtime if OP-TEE is loaded */ - .ep_info.pc = STM32MP_BL32_BASE, - - .ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, - SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_PLAT_SETUP), - - /* Updated at runtime if OP-TEE is loaded */ - .image_info.image_base = STM32MP_BL32_BASE, - .image_info.image_max_size = STM32MP_BL32_SIZE, - - .next_handoff_image_id = BL33_IMAGE_ID, - }, - -#if defined(AARCH32_SP_OPTEE) - /* Fill BL32 external 1 image related information */ - { - .image_id = BL32_EXTRA1_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, - /* Fill BL32 external 2 image related information */ - { - .image_id = BL32_EXTRA2_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - SECURE | NON_EXECUTABLE), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, - IMAGE_ATTRIB_SKIP_LOADING), - - .next_handoff_image_id = INVALID_IMAGE_ID, - }, -#endif /* AARCH32_SP_OPTEE */ - - /* Fill BL33 related information */ - { - .image_id = BL33_IMAGE_ID, - - SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, - VERSION_2, entry_point_info_t, - NON_SECURE | EXECUTABLE), - - .ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET, - .ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, - SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS), - - SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, - VERSION_2, image_info_t, 0U), - - .image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET, - .image_info.image_max_size = STM32MP_DDR_MAX_SIZE - - (PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE), - - .next_handoff_image_id = INVALID_IMAGE_ID, - } -}; - -REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c index f68eb3869..c4048fc08 100644 --- a/plat/st/stm32mp1/plat_image_load.c +++ b/plat/st/stm32mp1/plat_image_load.c @@ -4,12 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <assert.h> - #include <common/desc_image_load.h> -#include <plat/common/platform.h> - -#include <platform_def.h> /******************************************************************************* * This function flushes the data structures so that they are visible @@ -25,17 +20,6 @@ void plat_flush_next_bl_params(void) ******************************************************************************/ bl_load_info_t *plat_get_bl_image_load_info(void) { -#if STM32MP_USE_STM32IMAGE - bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID); - uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size(); - - assert(bl33 != NULL); - - /* Max size is non-secure DDR end address minus image_base */ - bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size - - bl33->image_info.image_base; -#endif /* STM32MP_USE_STM32IMAGE */ - return get_bl_load_info_from_mem_params_desc(); } diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 594fe0b32..7eecf3040 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -13,11 +13,6 @@ STM32MP_EARLY_CONSOLE ?= 0 STM32MP_RECONFIGURE_CONSOLE ?= 0 STM32MP_UART_BAUDRATE ?= 115200 -# Allow TF-A to concatenate BL2 & BL32 binaries in a single file, -# share DTB file between BL2 and BL32 -# If it is set to 0, then FIP is used -STM32MP_USE_STM32IMAGE ?= 0 - TRUSTED_BOARD_BOOT ?= 0 STM32MP_USE_EXTERNAL_HEAP ?= 0 @@ -117,7 +112,6 @@ STM32_TF_A_COPIES := 2 PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4))) ifeq (${PSA_FWU_SUPPORT},1) -ifneq (${STM32MP_USE_STM32IMAGE},1) # Number of banks of updatable firmware NR_OF_FW_BANKS := 2 NR_OF_IMAGES_IN_FW_BANK := 1 @@ -127,9 +121,6 @@ ifeq ($(shell test $(FWU_MAX_PART) -gt $(PLAT_PARTITION_MAX_ENTRIES); echo $$?), $(error "Required partition number is $(FWU_MAX_PART) where PLAT_PARTITION_MAX_ENTRIES is only \ $(PLAT_PARTITION_MAX_ENTRIES)") endif -else -$(error FWU Feature enabled only with FIP images) -endif endif ifeq ($(STM32MP13),1) @@ -160,14 +151,6 @@ ifeq ($(STM32MP13),1) BL2_DTSI := stm32mp13-bl2.dtsi FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) else -ifeq ($(STM32MP_USE_STM32IMAGE),1) -ifeq ($(AARCH32_SP),optee) -BL2_DTSI := stm32mp15-bl2.dtsi -FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) -else -FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME))) -endif -else BL2_DTSI := stm32mp15-bl2.dtsi FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) ifeq ($(AARCH32_SP),sp_min) @@ -175,7 +158,6 @@ BL32_DTSI := stm32mp15-bl32.dtsi FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME))) endif endif -endif $(eval DTC_V = $(shell $(DTC) -v | awk '{print $$NF}')) $(eval DTC_VERSION = $(shell printf "%d" $(shell echo ${DTC_V} | cut -d- -f1 | sed "s/\./0/g" | grep -o "[0-9]*"))) @@ -202,7 +184,6 @@ STM32IMAGEPATH ?= tools/stm32image STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT} STM32IMAGE_SRC := ${STM32IMAGEPATH}/stm32image.c -ifneq (${STM32MP_USE_STM32IMAGE},1) FIP_DEPS += dtbs STM32MP_HW_CONFIG := ${BL33_CFG} STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) @@ -232,7 +213,6 @@ ifneq ($(BL32_EXTRA2),) $(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2,,$(ENCRYPT_BL32))) endif endif -endif # Enable flags for C files $(eval $(call assert_booleans,\ @@ -255,7 +235,6 @@ $(eval $(call assert_booleans,\ STM32MP_UART_PROGRAMMER \ STM32MP_USB_PROGRAMMER \ STM32MP_USE_EXTERNAL_HEAP \ - STM32MP_USE_STM32IMAGE \ STM32MP13 \ STM32MP15 \ ))) @@ -299,7 +278,6 @@ $(eval $(call add_defines,\ STM32MP_UART_PROGRAMMER \ STM32MP_USB_PROGRAMMER \ STM32MP_USE_EXTERNAL_HEAP \ - STM32MP_USE_STM32IMAGE \ STM32MP13 \ STM32MP15 \ ))) @@ -308,11 +286,7 @@ $(eval $(call add_defines,\ PLAT_INCLUDES := -Iplat/st/common/include/ PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ -ifeq (${STM32MP_USE_STM32IMAGE},1) -include common/fdt_wrappers.mk -else include lib/fconf/fconf.mk -endif include lib/libfdt/libfdt.mk PLAT_BL_COMMON_SOURCES := common/uuid.c \ @@ -359,7 +333,6 @@ else PLAT_BL_COMMON_SOURCES += drivers/st/clk/stm32mp1_clk.c endif -ifneq (${STM32MP_USE_STM32IMAGE},1) BL2_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES} BL2_SOURCES += drivers/io/io_fip.c \ @@ -367,15 +340,6 @@ BL2_SOURCES += drivers/io/io_fip.c \ plat/st/common/stm32mp_fconf_io.c \ plat/st/stm32mp1/plat_bl2_mem_params_desc.c \ plat/st/stm32mp1/stm32mp1_fconf_firewall.c -else -BL2_SOURCES += ${FDT_WRAPPERS_SOURCES} - -BL2_SOURCES += drivers/io/io_dummy.c \ - drivers/st/io/io_stm32image.c \ - plat/st/common/bl2_stm32_io_storage.c \ - plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c \ - plat/st/stm32mp1/stm32mp1_security.c -endif include lib/zlib/zlib.mk @@ -541,13 +505,6 @@ check_dtc_version: false; \ fi -ifeq ($(STM32MP_USE_STM32IMAGE)-$(AARCH32_SP),1-sp_min) -${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP} - @echo " AS stm32mp1.S" - ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \ - -DDTB_BIN_PATH=\"$<\" \ - -c $(word 2,$^) -o $@ -else # Create DTB file for BL2 ${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | ${BUILD_PLAT} fdt_dirs @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ @@ -569,7 +526,6 @@ ${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%-bl2.dtb plat/st/stm32mp1/stm32m ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \ -DDTB_BIN_PATH=\"$<\" \ -c plat/st/stm32mp1/stm32mp1.S -o $@ -endif $(eval $(call MAKE_LD,${STM32_TF_LINKERFILE},plat/st/stm32mp1/stm32mp1.ld.S,bl2)) diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk index c3fc2cb39..1d754d980 100644 --- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk @@ -10,11 +10,9 @@ endif SP_MIN_WITH_SECURE_FIQ := 1 -ifneq ($(STM32MP_USE_STM32IMAGE),1) override ENABLE_PIE := 1 BL32_CFLAGS += -fpie -DENABLE_PIE BL32_LDFLAGS += $(PIE_LDFLAGS) -endif BL32_CFLAGS += -DSTM32MP_SHARED_RESOURCES diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c index 325666f95..50b079471 100644 --- a/plat/st/stm32mp1/sp_min/sp_min_setup.c +++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c @@ -115,11 +115,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { bl_params_t *params_from_bl2 = (bl_params_t *)arg0; -#if STM32MP_USE_STM32IMAGE - uintptr_t dt_addr = STM32MP_DTB_BASE; -#else uintptr_t dt_addr = arg1; -#endif stm32mp_setup_early_console(); diff --git a/plat/st/stm32mp1/stm32mp1.S b/plat/st/stm32mp1/stm32mp1.S index 85caa0a80..aee4f0ec2 100644 --- a/plat/st/stm32mp1/stm32mp1.S +++ b/plat/st/stm32mp1/stm32mp1.S @@ -1,16 +1,9 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#if STM32MP_USE_STM32IMAGE -#ifdef BL32_BIN_PATH -.section .bl32_image -.incbin BL32_BIN_PATH -#endif -#endif /* STM32MP_USE_STM32IMAGE */ - .section .bl2_image .incbin BL2_BIN_PATH diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S index 2254feead..1be82193b 100644 --- a/plat/st/stm32mp1/stm32mp1.ld.S +++ b/plat/st/stm32mp1/stm32mp1.ld.S @@ -43,11 +43,7 @@ SECTIONS * The strongest and only alignment contraint is MMU 4K page. * Indeed as images below will be removed, 4K pages will be re-used. */ -#if STM32MP_USE_STM32IMAGE - . = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE ); -#else . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE ); -#endif /* STM32MP_USE_STM32IMAGE */ __DTB_IMAGE_START__ = .; *(.dtb_image*) __DTB_IMAGE_END__ = .; @@ -66,18 +62,6 @@ SECTIONS *(.bl2_image*) __BL2_IMAGE_END__ = .; -#if STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) - /* - * bl32 will be settled by bl2. - * The strongest and only alignment constraint is 8 words to simplify - * memraise8 assembly code. - */ - . = ( STM32MP_BL32_BASE - STM32MP_BINARY_BASE ); - __BL32_IMAGE_START__ = .; - *(.bl32_image*) - __BL32_IMAGE_END__ = .; -#endif /* STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) */ - __DATA_END__ = .; } >RAM diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 5d7c2ffea..f0d85263e 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -26,11 +26,7 @@ #include <stm32mp1_shared_resources.h> #endif -#if !STM32MP_USE_STM32IMAGE #include "stm32mp1_fip_def.h" -#else /* STM32MP_USE_STM32IMAGE */ -#include "stm32mp1_stm32image_def.h" -#endif /* STM32MP_USE_STM32IMAGE */ /******************************************************************************* * CHIP ID diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index c40e045e8..9bdb07552 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -697,29 +697,6 @@ uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) } #endif -#if STM32MP_USE_STM32IMAGE -/* Get the non-secure DDR size */ -uint32_t stm32mp_get_ddr_ns_size(void) -{ - static uint32_t ddr_ns_size; - uint32_t ddr_size; - - if (ddr_ns_size != 0U) { - return ddr_ns_size; - } - - ddr_size = dt_get_ddr_size(); - if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || - (ddr_size > STM32MP_DDR_MAX_SIZE)) { - panic(); - } - - ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); - - return ddr_ns_size; -} -#endif /* STM32MP_USE_STM32IMAGE */ - void stm32_save_boot_interface(uint32_t interface, uint32_t instance) { uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); @@ -767,7 +744,7 @@ void stm32_save_boot_auth(uint32_t auth_status, uint32_t boot_partition) clk_disable(RTCAPB); } -#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT +#if PSA_FWU_SUPPORT void stm32mp1_fwu_set_boot_idx(void) { clk_enable(RTCAPB); @@ -808,4 +785,4 @@ void stm32_set_max_fwu_trial_boot_cnt(void) TAMP_BOOT_FWU_INFO_CNT_MSK); clk_disable(RTCAPB); } -#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ +#endif /* PSA_FWU_SUPPORT */ diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c deleted file mode 100644 index c84bffcf9..000000000 --- a/plat/st/stm32mp1/stm32mp1_security.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stdint.h> - -#include <platform_def.h> - -#include <common/debug.h> -#include <drivers/arm/tzc400.h> -#include <drivers/clk.h> -#include <drivers/st/stm32mp1_clk.h> -#include <dt-bindings/clock/stm32mp1-clks.h> -#include <dt-bindings/soc/stm32mp15-tzc400.h> -#include <lib/mmio.h> - -static unsigned int region_nb; - -static void init_tzc400_begin(unsigned int region0_attr) -{ - tzc400_init(STM32MP1_TZC_BASE); - tzc400_disable_filters(); - - /* Region 0 set to cover all DRAM at 0xC000_0000 */ - tzc400_configure_region0(region0_attr, 0); - - region_nb = 1U; -} - -static void init_tzc400_end(unsigned int action) -{ - tzc400_set_action(action); - tzc400_enable_filters(); -} - -static void tzc400_add_region(unsigned long long region_base, - unsigned long long region_top, bool sec) -{ - unsigned int sec_attr; - unsigned int nsaid_permissions; - - if (sec) { - sec_attr = TZC_REGION_S_RDWR; - nsaid_permissions = 0; - } else { - sec_attr = TZC_REGION_S_NONE; - nsaid_permissions = TZC_REGION_NSEC_ALL_ACCESS_RDWR; - } - - tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, region_nb, region_base, - region_top, sec_attr, nsaid_permissions); - - region_nb++; -} - -/******************************************************************************* - * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access - * and allow Non-Secure masters full access. - ******************************************************************************/ -static void init_tzc400(void) -{ - unsigned long long region_base, region_top; - unsigned long long ddr_base = STM32MP_DDR_BASE; - unsigned long long ddr_ns_size = - (unsigned long long)stm32mp_get_ddr_ns_size(); - unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U); - unsigned long long ddr_top __unused; - - init_tzc400_begin(TZC_REGION_S_NONE); - - /* - * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the - * same configuration to all filters in the TZC. - */ - region_base = ddr_base; - region_top = ddr_ns_top; - tzc400_add_region(region_base, region_top, false); - -#ifdef AARCH32_SP_OPTEE - /* Region 2 set to cover all secure DRAM. */ - region_base = region_top + 1U; - region_top += STM32MP_DDR_S_SIZE; - tzc400_add_region(region_base, region_top, true); - - ddr_top = STM32MP_DDR_BASE + dt_get_ddr_size() - 1U; - if (region_top < ddr_top) { - /* Region 3 set to cover non-secure memory DRAM after BL32. */ - region_base = region_top + 1U; - region_top = ddr_top; - tzc400_add_region(region_base, region_top, false); - } -#endif - - /* - * Raise an interrupt (secure FIQ) if a NS device tries to access - * secure memory - */ - init_tzc400_end(TZC_ACTION_INT); -} - -/******************************************************************************* - * Initialize the TrustZone Controller. - * Early initialization create only one region with full access to secure. - * This setting is used before and during DDR initialization. - ******************************************************************************/ -static void early_init_tzc400(void) -{ - clk_enable(TZC1); - clk_enable(TZC2); - - /* Region 0 set to cover all DRAM secure at 0xC000_0000 */ - init_tzc400_begin(TZC_REGION_S_RDWR); - - /* Raise an exception if a NS device tries to access secure memory */ - init_tzc400_end(TZC_ACTION_ERR); -} - -/******************************************************************************* - * Initialize the secure environment. At this moment only the TrustZone - * Controller is initialized. - ******************************************************************************/ -void stm32mp1_arch_security_setup(void) -{ - early_init_tzc400(); -} - -/******************************************************************************* - * Initialize the secure environment. At this moment only the TrustZone - * Controller is initialized. - ******************************************************************************/ -void stm32mp1_security_setup(void) -{ - init_tzc400(); -} diff --git a/plat/st/stm32mp1/stm32mp1_stm32image_def.h b/plat/st/stm32mp1/stm32mp1_stm32image_def.h deleted file mode 100644 index 6260cb903..000000000 --- a/plat/st/stm32mp1/stm32mp1_stm32image_def.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef STM32MP1_STM32IMAGE_DEF_H -#define STM32MP1_STM32IMAGE_DEF_H - -#ifdef AARCH32_SP_OPTEE -#if STM32MP15_OPTEE_RSV_SHM -#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ -#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ -#else -#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */ -#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */ -#endif -#else -#define STM32MP_DDR_S_SIZE U(0) -#define STM32MP_DDR_SHMEM_SIZE U(0) -#endif - -#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */ -#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ - -#ifdef AARCH32_SP_OPTEE -#define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE - -#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ - STM32MP_SEC_SYSRAM_SIZE - \ - STM32MP_BL2_SIZE) - -/* OP-TEE loads from SYSRAM base to BL2 DTB start address */ -#define STM32MP_OPTEE_BASE STM32MP_BL32_BASE -#define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ - STM32MP_BL2_SIZE - STM32MP_DTB_SIZE) -#define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE -#else /* AARCH32_SP_OPTEE */ -#define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */ - -#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \ - STM32MP_SEC_SYSRAM_SIZE - \ - STM32MP_BL32_SIZE) - -#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ - STM32MP_BL2_SIZE) -#endif /* AARCH32_SP_OPTEE */ - -/* DTB initialization value */ -#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ - STM32MP_DTB_SIZE) - -/* - * MAX_MMAP_REGIONS is usually: - * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup - */ -#if defined(IMAGE_BL32) -#define MAX_MMAP_REGIONS 6 -#endif - -/******************************************************************************* - * STM32MP1 RAW partition offset for MTD devices - ******************************************************************************/ -#define STM32MP_NOR_BL33_OFFSET U(0x00080000) -#ifdef AARCH32_SP_OPTEE -#define STM32MP_NOR_TEEH_OFFSET U(0x00280000) -#define STM32MP_NOR_TEED_OFFSET U(0x002C0000) -#define STM32MP_NOR_TEEX_OFFSET U(0x00300000) -#endif - -#define STM32MP_NAND_BL33_OFFSET U(0x00200000) -#ifdef AARCH32_SP_OPTEE -#define STM32MP_NAND_TEEH_OFFSET U(0x00600000) -#define STM32MP_NAND_TEED_OFFSET U(0x00680000) -#define STM32MP_NAND_TEEX_OFFSET U(0x00700000) -#endif - -#endif /* STM32MP1_STM32IMAGE_DEF_H */ |