summaryrefslogtreecommitdiff
path: root/plat/st/stm32mp1/stm32mp1_pm.c
diff options
context:
space:
mode:
authorYann Gautier <yann.gautier@st.com>2019-02-14 10:53:33 +0100
committerYann Gautier <yann.gautier@st.com>2019-02-14 11:20:23 +0100
commit0d21680c35f328f1b793f0765760e994d883ff12 (patch)
treec6e8b6e242aee14fbae6171261a63d31b5759b9d /plat/st/stm32mp1/stm32mp1_pm.c
parent5202cb393da7f6f3a9cf48a49e2a12f3bdee2b16 (diff)
downloadarm-trusted-firmware-0d21680c35f328f1b793f0765760e994d883ff12.tar.gz
stm32mp1: update clock driver
Remove useless private structure in function prototypes. Add a reference counter on clocks. Prepare for future secured/shared/non-secured clocks. Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Diffstat (limited to 'plat/st/stm32mp1/stm32mp1_pm.c')
-rw-r--r--plat/st/stm32mp1/stm32mp1_pm.c14
1 files changed, 2 insertions, 12 deletions
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 3262607a5..cf9fa8e69 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -59,7 +59,6 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state)
static int stm32_pwr_domain_on(u_register_t mpidr)
{
unsigned long current_cpu_mpidr = read_mpidr_el1();
- uint32_t tamp_clk_off = 0;
uint32_t bkpr_core1_addr =
tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
uint32_t bkpr_core1_magic =
@@ -75,12 +74,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
return PSCI_E_INVALID_ADDRESS;
}
- if (!stm32mp_clk_is_enabled(RTCAPB)) {
- tamp_clk_off = 1;
- if (stm32mp_clk_enable(RTCAPB) != 0) {
- panic();
- }
- }
+ stm32mp_clk_enable(RTCAPB);
cntfrq_core0 = read_cntfrq_el0();
@@ -90,11 +84,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
/* Write magic number in backup register */
mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
- if (tamp_clk_off != 0U) {
- if (stm32mp_clk_disable(RTCAPB) != 0) {
- panic();
- }
- }
+ stm32mp_clk_disable(RTCAPB);
/* Generate an IT to core 1 */
gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU);