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| author | Graeme Gregory <graeme@nuviainc.com> | 2020-08-28 16:37:02 +0100 |
|---|---|---|
| committer | Graeme Gregory <graeme@nuviainc.com> | 2021-01-19 18:40:05 +0000 |
| commit | 5565ede44a80805789d375aaae2773e02119cf9b (patch) | |
| tree | 24ab657960030061f0b2c957a4cef2a4b5e66950 /plat/qemu/qemu_sbsa/include | |
| parent | 916a7e11e2e78ff31114018b139874635fe8fc24 (diff) | |
| download | arm-trusted-firmware-5565ede44a80805789d375aaae2773e02119cf9b.tar.gz | |
qemu/qemu_sbsa: topology is different from qemu so add handling
sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topology file
and increase the BL31_SIZE to accommodate the bigger table sizes. Change
platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so
plat_helpers.S calculates correct result.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7
Diffstat (limited to 'plat/qemu/qemu_sbsa/include')
| -rw-r--r-- | plat/qemu/qemu_sbsa/include/platform_def.h | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h index 84710240d..94bf0d101 100644 --- a/plat/qemu/qemu_sbsa/include/platform_def.h +++ b/plat/qemu/qemu_sbsa/include/platform_def.h @@ -16,20 +16,17 @@ #define PLATFORM_STACK_SIZE 0x1000 -#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) +#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) /* * Define the number of cores per cluster used in calculating core position. * The cluster number is shifted by this value and added to the core ID, * so its value represents log2(cores/cluster). - * Default is 2**(2) = 4 cores per cluster. + * Default is 2**(3) = 8 cores per cluster. */ -#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2) -#define PLATFORM_CLUSTER_COUNT U(2) -#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ - PLATFORM_CLUSTER1_CORE_COUNT) - +#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(3) +#define PLATFORM_CLUSTER_COUNT U(64) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ + PLATFORM_MAX_CPUS_PER_CLUSTER) #define QEMU_PRIMARY_CPU U(0) #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ @@ -137,7 +134,7 @@ * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the * current BL3-1 debug size plus a little space for growth. */ -#define BL31_SIZE 0x50000 +#define BL31_SIZE 0x300000 #define BL31_BASE (BL31_LIMIT - BL31_SIZE) #define BL31_LIMIT (BL1_RW_BASE) #define BL31_PROGBITS_LIMIT BL1_RW_BASE |