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| author | Steven Kao <skao@nvidia.com> | 2017-11-14 18:52:05 +0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-01-23 10:32:57 -0800 |
| commit | c63ec2639aea24641da342a4b5bc7126762241f0 (patch) | |
| tree | 72cfe30f2ba8c19e777ffd709b74b6d5dd1e9af4 /plat/nvidia/tegra/soc/t186/plat_memctrl.c | |
| parent | 539c62d7b3d31612e4c6a4a9a1ba8fc80b3874c9 (diff) | |
| download | arm-trusted-firmware-c63ec2639aea24641da342a4b5bc7126762241f0.tar.gz | |
Tegra: memctrl_v2: platform handler for TZDRAM setup
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.
Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b
Signed-off-by: Steven Kao <skao@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc/t186/plat_memctrl.c')
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_memctrl.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c index 71904a8f6..376ee86df 100644 --- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c @@ -7,6 +7,7 @@ #include <assert.h> #include <common/bl_common.h> +#include <mce.h> #include <memctrl_v2.h> #include <tegra_mc_def.h> #include <tegra_platform.h> @@ -546,8 +547,15 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) { uint32_t val; - (void)phys_base; - (void)size_in_bytes; + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring TrustZone DRAM Memory Carveout\n"); + + tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); + tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); + tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); /* * When TZ encryption is enabled, we need to setup TZDRAM @@ -565,4 +573,10 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK; mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val); + + /* + * MCE propagates the security configuration values across the + * CCPLEX. + */ + (void)mce_update_gsc_tzdram(); } |