feat(mediatek): support coreboot BL31 loading

The ChromeOS project uses Coreboot as BL2 instead of MediaTek regular
bootloader, so we use COREBOOT flag to support Coreboot boot flow.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I45e95ea51e90158187452eba52fc58090d1c60a4

3 files changed, 68 insertions, 2 deletions

diff --git a/plat/mediatek/build_helpers/mtk_build_helpers.mk b/plat/mediatek/build_helpers/mtk_build_helpers.mk
index a5a4c3e36..fc3876e71 100644
--- a/plat/mediatek/build_helpers/mtk_build_helpers.mk
+++ b/plat/mediatek/build_helpers/mtk_build_helpers.mk
@@ -116,9 +116,13 @@ endef
 # Include MTK configuration files
 
 # MTK makefile variables
+ifeq (${COREBOOT},1)
+MTK_COMMON_CFG := $(MTK_PLAT)/common/coreboot_config.mk
+else
+MTK_COMMON_CFG := $(MTK_PLAT)/common/common_config.mk
+endif
 MTK_PLAT      := plat/mediatek
 MTK_PLAT_SOC  := ${MTK_PLAT}/${MTK_SOC}
-MTK_COMMON_CFG := $(MTK_PLAT)/common/common_config.mk
 MTK_PLAT_CFG := $(MTK_PLAT_SOC)/plat_config.mk
 MTK_PROJECT_CFG := $(MTK_PLAT)/project/$(PLAT)/project_config.mk
 MTK_OPTIONS := $(MTK_PLAT)/build_helpers/options.mk
diff --git a/plat/mediatek/common/coreboot_config.mk b/plat/mediatek/common/coreboot_config.mk
new file mode 100644
index 000000000..59d18e86d
--- /dev/null
+++ b/plat/mediatek/common/coreboot_config.mk
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# indicate the reset vector address can be programmed
+PROGRAMMABLE_RESET_ADDRESS := 1
+COLD_BOOT_SINGLE_CPU := 1
+# Build flag to include AArch32 registers in cpu context save and restore during
+# world switch. This flag must be set to 0 for AArch64-only platforms.
+CTX_INCLUDE_AARCH32_REGS := 0
+PLAT_XLAT_TABLES_DYNAMIC := 1
+
+VENDOR_EXTEND_PUBEVENT_ENABLE := 1
diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c
index 46f7a634c..79ab29d6f 100644
--- a/plat/mediatek/common/mtk_bl31_setup.c
+++ b/plat/mediatek/common/mtk_bl31_setup.c
@@ -15,6 +15,14 @@
 #endif
 #include <plat/common/platform.h>
 
+#if COREBOOT
+#include <common/desc_image_load.h>
+
+#include <drivers/ti/uart/uart_16550.h>
+#include <lib/coreboot.h>
+#include <plat_params.h>
+#endif
+
 /* MTK headers */
 #if MTK_SIP_KERNEL_BOOT_ENABLE
 #include <cold_boot.h>
@@ -24,6 +32,32 @@
 
 IMPORT_SYM(uintptr_t, __RW_START__, RW_START);
 IMPORT_SYM(uintptr_t, __DATA_START__, DATA_START);
+
+#if COREBOOT
+static entry_point_info_t bl32_ep_info;
+static entry_point_info_t bl33_ep_info;
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+	entry_point_info_t *next_image_info;
+
+	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+	assert(next_image_info->h.type == PARAM_EP);
+
+	/* None of the images on this platform can have 0x0 as the entrypoint */
+	if (next_image_info->pc) {
+		return next_image_info;
+	} else {
+		return NULL;
+	}
+}
+#else
 #ifndef MTK_BL31_AS_BL2
 static struct mtk_bl31_fw_config bl31_fw_config;
 #else
@@ -55,7 +89,7 @@ void *get_mtk_bl31_fw_config(int index)
 	}
 	return arg;
 }
-
+#endif
 /*****************************************************************************
  * Perform the very early platform specific architectural setup shared between
  * ARM standard platforms. This only does basic initialization. Later
@@ -67,6 +101,18 @@ void bl31_early_platform_setup2(u_register_t from_bl2,
 				u_register_t hw_config, u_register_t plat_params_from_bl2)
 
 {
+#if COREBOOT
+	static console_t console;
+
+	params_early_setup(soc_fw_config);
+	if (coreboot_serial.type) {
+		console_16550_register(coreboot_serial.baseaddr,
+				       coreboot_serial.input_hertz,
+				       coreboot_serial.baud,
+				       &console);
+	}
+	bl31_params_parse_helper(from_bl2, &bl32_ep_info, &bl33_ep_info);
+#else
 	struct mtk_bl_param_t *p_mtk_bl_param = (struct mtk_bl_param_t *)from_bl2;
 
 	if (p_mtk_bl_param == NULL) {
@@ -78,6 +124,7 @@ void bl31_early_platform_setup2(u_register_t from_bl2,
 	bl31_fw_config.soc_fw_config = (void *)soc_fw_config;
 	bl31_fw_config.hw_config = (void *)hw_config;
 	bl31_fw_config.reserved = (void *)plat_params_from_bl2;
+#endif
 
 	INFO("MTK BL31 start\n");
 	/* Init delay function */