feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.

for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.

2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.

so add udelay 100 to safely clear the SRC bit 0.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I52e8e7739fdaaf86442bcd148e768b6af38bcdb7

1 files changed, 10 insertions, 2 deletions

diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c
index 367c9411d..fa83324e1 100644
--- a/plat/imx/imx8m/imx8mq/gpc.c
+++ b/plat/imx/imx8m/imx8mq/gpc.c
@@ -9,6 +9,7 @@
 #include <stdbool.h>
 
 #include <common/debug.h>
+#include <drivers/delay_timer.h>
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
 #include <platform_def.h>
@@ -176,6 +177,13 @@ void imx_gpc_init(void)
 	mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
 	mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
 
-	/* enable all the power domain by default */
-	mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf);
+	/*
+	 * for USB OTG, the limitation are:
+	 * 1. before system clock config, the IPG clock run at 12.5MHz, delay time
+	 *    should be longer than 82us.
+	 * 2. after system clock config, ipg clock run at 66.5MHz, delay time
+	 *    be longer that 15.3 us.
+	 *    Add 100us to make sure the USB OTG SRC is clear safely.
+	 */
+	udelay(100);
 }