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| author | Elyes Haouas <ehaouas@noos.fr> | 2023-02-13 09:14:48 +0100 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2023-05-09 15:57:12 +0100 |
| commit | 1b491eead580d7849a45a38f2c6a935a5d8d1160 (patch) | |
| tree | 5085dd0af7deed3a5a52dbcd82a78aa5cd96e888 /plat/imx/imx8m/imx8mp/gpc.c | |
| parent | 8557d491b6dbd6cbf27cc2ae6425f6cb29ca2c35 (diff) | |
| download | arm-trusted-firmware-1b491eead580d7849a45a38f2c6a935a5d8d1160.tar.gz | |
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
Diffstat (limited to 'plat/imx/imx8m/imx8mp/gpc.c')
| -rw-r--r-- | plat/imx/imx8m/imx8mp/gpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index 452e7883c..956b50817 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -337,7 +337,7 @@ void imx_gpc_init(void) /* * Set the CORE & SCU power up timing: * SW = 0x1, SW2ISO = 0x1; - * the CPU CORE and SCU power up timming counter + * the CPU CORE and SCU power up timing counter * is drived by 32K OSC, each domain's power up * latency is (SW + SW2ISO) / 32768 */ |