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| author | Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> | 2021-07-08 09:35:57 +0100 |
|---|---|---|
| committer | Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> | 2021-07-23 10:33:59 +0100 |
| commit | 68ac5ed0493b24e6a0a178171a47db75a31cc423 (patch) | |
| tree | 9034048bd8ec2cc7abc7f1b8e2b541a194be9602 /lib/el3_runtime/aarch64/context.S | |
| parent | 52eb322919017b4230fb0f9580020375db56466b (diff) | |
| download | arm-trusted-firmware-68ac5ed0493b24e6a0a178171a47db75a31cc423.tar.gz | |
fix(el3_runtime): fix SVE and AMU extension enablement flags
If SVE are enabled for both Non-secure and Secure world along with AMU
extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit
from bl31. This restricts access to the AMU register set in normal
world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT
by saving and restoring CPTR_EL3 register from EL3 context.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
Diffstat (limited to 'lib/el3_runtime/aarch64/context.S')
| -rw-r--r-- | lib/el3_runtime/aarch64/context.S | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index d610fd492..40e7ddfa1 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -903,16 +903,11 @@ func el3_exit #if IMAGE_BL31 /* ---------------------------------------------------------- - * Restore CPTR_EL3, ZCR_EL3 for SVE support. - * If SVE is not supported - skip the restoration. + * Restore CPTR_EL3. * ZCR is only restored if SVE is supported and enabled. * Synchronization is required before zcr_el3 is addressed. * ---------------------------------------------------------- */ - mrs x17, id_aa64pfr0_el1 - ubfx x17, x17, ID_AA64PFR0_SVE_SHIFT, ID_AA64PFR0_SVE_LENGTH - cbz x17, sve_not_enabled - ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3] msr cptr_el3, x19 |