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| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-02-28 14:51:28 -0600 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2023-03-08 14:58:05 -0600 |
| commit | a63332c517ac5699644d3e2fbf159d3e35c32549 (patch) | |
| tree | 1e0ee8949a3472fae36f430b02ee3ad362b60101 /include | |
| parent | 2b7150b381f3497d391ec28e2f34be01b2968ada (diff) | |
| download | arm-trusted-firmware-a63332c517ac5699644d3e2fbf159d3e35c32549.tar.gz | |
fix(cpus): workaround for Cortex-A78 erratum 2742426
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a78.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index fb325b6d7..66f565d4a 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -20,8 +20,8 @@ #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) #define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) -#define CPUECTLR_EL1_PF_MODE_LSB U(6) -#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions @@ -42,6 +42,8 @@ #define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2 +#define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0 + /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. ******************************************************************************/ |