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| author | Juan Pablo Conde <juanpablo.conde@arm.com> | 2022-07-12 16:40:29 -0400 |
|---|---|---|
| committer | Juan Pablo Conde <juanpablo.conde@arm.com> | 2022-08-18 15:53:54 -0400 |
| commit | ff86e0b4e6c34d28b8642dd8eb9cbdd517bad195 (patch) | |
| tree | 3bd2509c4c468311bc6844e9428b00de3aa9f0aa /include/arch/aarch64/arch.h | |
| parent | 17e76b5eb7901534ff9ee3f62b9990ba6038b002 (diff) | |
| download | arm-trusted-firmware-ff86e0b4e6c34d28b8642dd8eb9cbdd517bad195.tar.gz | |
feat(rng-trap): add EL3 support for FEAT_RNG_TRAP
FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This patch adds a new build flag
ENABLE_FEAT_RNG_TRAP that enables the feature.
This feature is supported only in AArch64 state from Armv8.5 onwards.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index e55d33fd3..3a2a032fd 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -353,6 +353,12 @@ #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) +#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) +#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) + +#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) +#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) + /* Memory Tagging Extension is not implemented */ #define MTE_UNIMPLEMENTED U(0) /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ @@ -485,6 +491,7 @@ #define SCR_GPF_BIT (UL(1) << 48) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) +#define SCR_TRNDR_BIT (UL(1) << 40) #define SCR_HXEn_BIT (UL(1) << 38) #define SCR_ENTP2_SHIFT U(41) #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) |